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Merge branch 'next-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc into test

Browse source 
Merge miscellaneous bits from benh. Fix a minor conflict with
OpalMessageType changing names to opal_msg_type.
This commit is contained in:
Michael Ellerman 2015-03-26 20:03:16 +11:00
commit df60f57684
13 changed files with 71 additions and 168 deletions
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3
arch/powerpc/include/asm/cache.h
View file

@ -76,9 +76,6 @@ extern void _set_L3CR(unsigned long);
#define _set_L3CR(val) do { } while(0)
#endif
extern void cacheable_memzero(void *p, unsigned int nb);
extern void *cacheable_memcpy(void *, const void *, unsigned int);
#endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_CACHE_H */

2
arch/powerpc/include/asm/opal.h
View file

@ -210,6 +210,8 @@ extern int opal_notifier_unregister(struct notifier_block *nb);
extern int opal_message_notifier_register(enum opal_msg_type msg_type,
struct notifier_block *nb);
extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
struct notifier_block *nb);
extern void opal_notifier_enable(void);
extern void opal_notifier_disable(void);
extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);

127
arch/powerpc/lib/copy_32.S
View file

@ -69,54 +69,6 @@ CACHELINE_BYTES = L1_CACHE_BYTES
LG_CACHELINE_BYTES = L1_CACHE_SHIFT
CACHELINE_MASK = (L1_CACHE_BYTES-1)
/*
* Use dcbz on the complete cache lines in the destination
* to set them to zero. This requires that the destination
* area is cacheable. -- paulus
*/
_GLOBAL(cacheable_memzero)
mr r5,r4
li r4,0
addi r6,r3,-4
cmplwi 0,r5,4
blt 7f
stwu r4,4(r6)
beqlr
andi. r0,r6,3
add r5,r0,r5
subf r6,r0,r6
clrlwi r7,r6,32-LG_CACHELINE_BYTES
add r8,r7,r5
srwi r9,r8,LG_CACHELINE_BYTES
addic. r9,r9,-1 /* total number of complete cachelines */
ble 2f
xori r0,r7,CACHELINE_MASK & ~3
srwi. r0,r0,2
beq 3f
mtctr r0
4: stwu r4,4(r6)
bdnz 4b
3: mtctr r9
li r7,4
10: dcbz r7,r6
addi r6,r6,CACHELINE_BYTES
bdnz 10b
clrlwi r5,r8,32-LG_CACHELINE_BYTES
addi r5,r5,4
2: srwi r0,r5,2
mtctr r0
bdz 6f
1: stwu r4,4(r6)
bdnz 1b
6: andi. r5,r5,3
7: cmpwi 0,r5,0
beqlr
mtctr r5
addi r6,r6,3
8: stbu r4,1(r6)
bdnz 8b
blr
_GLOBAL(memset)
rlwimi r4,r4,8,16,23
rlwimi r4,r4,16,0,15
@ -142,85 +94,6 @@ _GLOBAL(memset)
bdnz 8b
blr
/*
* This version uses dcbz on the complete cache lines in the
* destination area to reduce memory traffic. This requires that
* the destination area is cacheable.
* We only use this version if the source and dest don't overlap.
* -- paulus.
*/
_GLOBAL(cacheable_memcpy)
add r7,r3,r5 /* test if the src & dst overlap */
add r8,r4,r5
cmplw 0,r4,r7
cmplw 1,r3,r8
crand 0,0,4 /* cr0.lt &= cr1.lt */
blt memcpy /* if regions overlap */
addi r4,r4,-4
addi r6,r3,-4
neg r0,r3
andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
beq 58f
cmplw 0,r5,r0 /* is this more than total to do? */
blt 63f /* if not much to do */
andi. r8,r0,3 /* get it word-aligned first */
subf r5,r0,r5
mtctr r8
beq+ 61f
70: lbz r9,4(r4) /* do some bytes */
stb r9,4(r6)
addi r4,r4,1
addi r6,r6,1
bdnz 70b
61: srwi. r0,r0,2
mtctr r0
beq 58f
72: lwzu r9,4(r4) /* do some words */
stwu r9,4(r6)
bdnz 72b
58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
clrlwi r5,r5,32-LG_CACHELINE_BYTES
li r11,4
mtctr r0
beq 63f
53:
dcbz r11,r6
COPY_16_BYTES
#if L1_CACHE_BYTES >= 32
COPY_16_BYTES
#if L1_CACHE_BYTES >= 64
COPY_16_BYTES
COPY_16_BYTES
#if L1_CACHE_BYTES >= 128
COPY_16_BYTES
COPY_16_BYTES
COPY_16_BYTES
COPY_16_BYTES
#endif
#endif
#endif
bdnz 53b
63: srwi. r0,r5,2
mtctr r0
beq 64f
30: lwzu r0,4(r4)
stwu r0,4(r6)
bdnz 30b
64: andi. r0,r5,3
mtctr r0
beq+ 65f
40: lbz r0,4(r4)
stb r0,4(r6)
addi r4,r4,1
addi r6,r6,1
bdnz 40b
65: blr
_GLOBAL(memmove)
cmplw 0,r3,r4
bgt backwards_memcpy

1
arch/powerpc/lib/locks.c
View file

@ -41,6 +41,7 @@ void __spin_yield(arch_spinlock_t *lock)
plpar_hcall_norets(H_CONFER,
get_hard_smp_processor_id(holder_cpu), yield_count);
}
EXPORT_SYMBOL_GPL(__spin_yield);
/*
* Waiting for a read lock or a write lock on a rwlock...

4
arch/powerpc/lib/ppc_ksyms.c
View file

@ -8,10 +8,6 @@ EXPORT_SYMBOL(memset);
EXPORT_SYMBOL(memmove);
EXPORT_SYMBOL(memcmp);
EXPORT_SYMBOL(memchr);
#ifdef CONFIG_PPC32
EXPORT_SYMBOL(cacheable_memcpy);
EXPORT_SYMBOL(cacheable_memzero);
#endif
EXPORT_SYMBOL(strcpy);
EXPORT_SYMBOL(strncpy);

2
arch/powerpc/mm/ppc_mmu_32.c
View file

@ -224,7 +224,7 @@ void __init MMU_init_hw(void)
*/
if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
Hash = __va(memblock_alloc(Hash_size, Hash_size));
cacheable_memzero(Hash, Hash_size);
memset(Hash, 0, Hash_size);
_SDR1 = __pa(Hash) | SDR1_LOW_BITS;
Hash_end = (struct hash_pte *) ((unsigned long)Hash + Hash_size);

2
arch/powerpc/platforms/powermac/bootx_init.c
View file

@ -246,7 +246,7 @@ static void __init bootx_scan_dt_build_strings(unsigned long base,
DBG(" detected display ! adding properties names !\n");
bootx_dt_add_string("linux,boot-display", mem_end);
bootx_dt_add_string("linux,opened", mem_end);
strncpy(bootx_disp_path, namep, 255);
strlcpy(bootx_disp_path, namep, sizeof(bootx_disp_path));
}
/* get and store all property names */

3
arch/powerpc/platforms/powermac/pic.c
View file

@ -321,6 +321,9 @@ static void __init pmac_pic_probe_oldstyle(void)
max_irqs = max_real_irqs = 64;
/* We might have a second cascaded heathrow */
/* Compensate for of_node_put() in of_find_node_by_name() */
of_node_get(master);
slave = of_find_node_by_name(master, "mac-io");
/* Check ordering of master & slave */

6
arch/powerpc/platforms/powernv/opal-flash.c
View file

@ -120,7 +120,11 @@ static struct image_header_t image_header;
static struct image_data_t image_data;
static struct validate_flash_t validate_flash_data;
static struct manage_flash_t manage_flash_data;
static struct update_flash_t update_flash_data;
/* Initialize update_flash_data status to No Operation */
static struct update_flash_t update_flash_data = {
.status = FLASH_NO_OP,
};
static DEFINE_MUTEX(image_data_mutex);

49
arch/powerpc/platforms/powernv/opal.c
View file

@ -23,6 +23,8 @@
#include <linux/kobject.h>
#include <linux/delay.h>
#include <linux/memblock.h>
#include <linux/kthread.h>
#include <linux/freezer.h>
#include <asm/machdep.h>
#include <asm/opal.h>
@ -58,6 +60,7 @@ static struct atomic_notifier_head opal_msg_notifier_head[OPAL_MSG_TYPE_MAX];
static DEFINE_SPINLOCK(opal_notifier_lock);
static uint64_t last_notified_mask = 0x0ul;
static atomic_t opal_notifier_hold = ATOMIC_INIT(0);
static uint32_t opal_heartbeat;
static void opal_reinit_cores(void)
{
@ -305,20 +308,23 @@ void opal_notifier_disable(void)
int opal_message_notifier_register(enum opal_msg_type msg_type,
struct notifier_block *nb)
{
if (!nb) {
pr_warning("%s: Invalid argument (%p)\n",
__func__, nb);
return -EINVAL;
}
if (msg_type > OPAL_MSG_TYPE_MAX) {
pr_warning("%s: Invalid message type argument (%d)\n",
if (!nb || msg_type >= OPAL_MSG_TYPE_MAX) {
pr_warning("%s: Invalid arguments, msg_type:%d\n",
__func__, msg_type);
return -EINVAL;
}
return atomic_notifier_chain_register(
&opal_msg_notifier_head[msg_type], nb);
}
int opal_message_notifier_unregister(enum opal_msg_type msg_type,
struct notifier_block *nb)
{
return atomic_notifier_chain_unregister(
&opal_msg_notifier_head[msg_type], nb);
}
static void opal_message_do_notify(uint32_t msg_type, void *msg)
{
/* notify subscribers */
@ -351,7 +357,7 @@ static void opal_handle_message(void)
type = be32_to_cpu(msg.msg_type);
/* Sanity check */
if (type > OPAL_MSG_TYPE_MAX) {
if (type >= OPAL_MSG_TYPE_MAX) {
pr_warning("%s: Unknown message type: %u\n", __func__, type);
return;
}
@ -744,6 +750,29 @@ static void __init opal_irq_init(struct device_node *dn)
}
}
static int kopald(void *unused)
{
set_freezable();
do {
try_to_freeze();
opal_poll_events(NULL);
msleep_interruptible(opal_heartbeat);
} while (!kthread_should_stop());
return 0;
}
static void opal_init_heartbeat(void)
{
/* Old firwmware, we assume the HVC heartbeat is sufficient */
if (of_property_read_u32(opal_node, "ibm,heartbeat-ms",
&opal_heartbeat) != 0)
opal_heartbeat = 0;
if (opal_heartbeat)
kthread_run(kopald, NULL, "kopald");
}
static int __init opal_init(void)
{
struct device_node *np, *consoles;
@ -772,6 +801,9 @@ static int __init opal_init(void)
/* Create i2c platform devices */
opal_i2c_create_devs();
/* Setup a heatbeat thread if requested by OPAL */
opal_init_heartbeat();
/* Find all OPAL interrupts and request them */
opal_irq_init(opal_node);
@ -794,6 +826,7 @@ static int __init opal_init(void)
opal_msglog_init();
}
/* Initialize OPAL IPMI backend */
opal_ipmi_init(opal_node);
return 0;

3
drivers/macintosh/smu.c
View file

@ -557,8 +557,7 @@ int __init smu_init (void)
return 0;
fail_msg_node:
if (smu->msg_node)
of_node_put(smu->msg_node);
of_node_put(smu->msg_node);
fail_db_node:
of_node_put(smu->db_node);
fail_bootmem:

25
drivers/macintosh/via-pmu.c
View file

@ -329,10 +329,11 @@ int __init find_via_pmu(void)
gaddr = of_translate_address(gpiop, reg);
if (gaddr != OF_BAD_ADDR)
gpio_reg = ioremap(gaddr, 0x10);
of_node_put(gpiop);
}
if (gpio_reg == NULL) {
printk(KERN_ERR "via-pmu: Can't find GPIO reg !\n");
goto fail_gpio;
goto fail;
}
} else
pmu_kind = PMU_UNKNOWN;
@ -340,7 +341,7 @@ int __init find_via_pmu(void)
via = ioremap(taddr, 0x2000);
if (via == NULL) {
printk(KERN_ERR "via-pmu: Can't map address !\n");
goto fail;
goto fail_via_remap;
}
out_8(&via[IER], IER_CLR | 0x7f); /* disable all intrs */
@ -348,10 +349,8 @@ int __init find_via_pmu(void)
pmu_state = idle;
if (!init_pmu()) {
via = NULL;
return 0;
}
if (!init_pmu())
goto fail_init;
printk(KERN_INFO "PMU driver v%d initialized for %s, firmware: %02x\n",
PMU_DRIVER_VERSION, pbook_type[pmu_kind], pmu_version);
@ -359,11 +358,15 @@ int __init find_via_pmu(void)
sys_ctrler = SYS_CTRLER_PMU;
return 1;
fail:
of_node_put(vias);
fail_init:
iounmap(via);
via = NULL;
fail_via_remap:
iounmap(gpio_reg);
gpio_reg = NULL;
fail_gpio:
fail:
of_node_put(vias);
vias = NULL;
return 0;
}
@ -2109,7 +2112,7 @@ pmu_read(struct file *file, char __user *buf,
spin_lock_irqsave(&pp->lock, flags);
add_wait_queue(&pp->wait, &wait);
current->state = TASK_INTERRUPTIBLE;
set_current_state(TASK_INTERRUPTIBLE);
for (;;) {
ret = -EAGAIN;
@ -2138,7 +2141,7 @@ pmu_read(struct file *file, char __user *buf,
schedule();
spin_lock_irqsave(&pp->lock, flags);
}
current->state = TASK_RUNNING;
__set_current_state(TASK_RUNNING);
remove_wait_queue(&pp->wait, &wait);
spin_unlock_irqrestore(&pp->lock, flags);

12
drivers/net/ethernet/ibm/emac/core.c
View file

@ -79,13 +79,6 @@ MODULE_AUTHOR
("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
MODULE_LICENSE("GPL");
/*
* PPC64 doesn't (yet) have a cacheable_memcpy
*/
#ifdef CONFIG_PPC64
#define cacheable_memcpy(d,s,n) memcpy((d),(s),(n))
#endif
/* minimum number of free TX descriptors required to wake up TX process */
#define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
@ -1673,7 +1666,7 @@ static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
dev_kfree_skb(dev->rx_sg_skb);
dev->rx_sg_skb = NULL;
} else {
cacheable_memcpy(skb_tail_pointer(dev->rx_sg_skb),
memcpy(skb_tail_pointer(dev->rx_sg_skb),
dev->rx_skb[slot]->data, len);
skb_put(dev->rx_sg_skb, len);
emac_recycle_rx_skb(dev, slot, len);
@ -1730,8 +1723,7 @@ static int emac_poll_rx(void *param, int budget)
goto oom;
skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
cacheable_memcpy(copy_skb->data - 2, skb->data - 2,
len + 2);
memcpy(copy_skb->data - 2, skb->data - 2, len + 2);
emac_recycle_rx_skb(dev, slot, len);
skb = copy_skb;
} else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))