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drm/amdgpu: export gfx config double offchip LDS buffers (v3)
v2: move the config struct to drm_amdgpu_info_device v3: move the config feature to amdgpu_gca_config Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6 changed files with 33 additions and 0 deletions
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@ -845,6 +845,9 @@ struct amdgpu_gca_config {
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uint32_t macrotile_mode_array[16];
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struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
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/* gfx configure feature */
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uint32_t double_offchip_lds_buf;
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};
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struct amdgpu_cu_info {
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@ -528,6 +528,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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dev_info.vram_type = adev->mc.vram_type;
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dev_info.vram_bit_width = adev->mc.vram_width;
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dev_info.vce_harvest_config = adev->vce.harvest_config;
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dev_info.gc_double_offchip_lds_buf =
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adev->gfx.config.double_offchip_lds_buf;
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return copy_to_user(out, &dev_info,
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min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
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@ -1579,6 +1579,11 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
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mutex_unlock(&adev->grbm_idx_mutex);
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}
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static void gfx_v6_0_config_init(struct amdgpu_device *adev)
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{
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adev->gfx.config.double_offchip_lds_buf = 1;
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}
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static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
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{
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u32 gb_addr_config = 0;
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@ -1736,6 +1741,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
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gfx_v6_0_setup_spi(adev);
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gfx_v6_0_get_cu_info(adev);
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gfx_v6_0_config_init(adev);
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WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
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(0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
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@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
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mutex_unlock(&adev->srbm_mutex);
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}
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static void gfx_v7_0_config_init(struct amdgpu_device *adev)
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{
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adev->gfx.config.double_offchip_lds_buf = 1;
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}
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/**
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* gfx_v7_0_gpu_init - setup the 3D engine
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*
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@ -1899,6 +1904,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
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gfx_v7_0_setup_rb(adev);
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gfx_v7_0_get_cu_info(adev);
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gfx_v7_0_config_init(adev);
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/* set HW defaults for 3D engine */
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WREG32(mmCP_MEQ_THRESHOLDS,
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@ -3846,6 +3846,19 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
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mutex_unlock(&adev->srbm_mutex);
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}
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static void gfx_v8_0_config_init(struct amdgpu_device *adev)
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{
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switch (adev->asic_type) {
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default:
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adev->gfx.config.double_offchip_lds_buf = 1;
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break;
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case CHIP_CARRIZO:
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case CHIP_STONEY:
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adev->gfx.config.double_offchip_lds_buf = 0;
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break;
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}
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}
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static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
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{
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u32 tmp;
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@ -3859,6 +3872,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
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gfx_v8_0_tiling_mode_table_init(adev);
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gfx_v8_0_setup_rb(adev);
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gfx_v8_0_get_cu_info(adev);
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gfx_v8_0_config_init(adev);
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/* XXX SH_MEM regs */
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/* where to put LDS, scratch, GPUVM in FSA64 space */
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@ -726,6 +726,8 @@ struct drm_amdgpu_info_device {
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__u32 vram_bit_width;
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/* vce harvesting instance */
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__u32 vce_harvest_config;
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/* gfx double offchip LDS buffers */
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__u32 gc_double_offchip_lds_buf;
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};
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struct drm_amdgpu_info_hw_ip {
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