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drm/i915/dvo: Extract intel_dvo_regs.h

Browse source 
Pull the DVO port register definitons into their own header
to declutter i915_reg.h a bit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221122120825.26338-10-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2022-11-22 14:08:24 +02:00
parent 079c4c0c6c
commit df9f0ebe87
3 changed files with 55 additions and 44 deletions
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1
drivers/gpu/drm/i915/display/intel_dvo.c
View file

@ -38,6 +38,7 @@
#include "intel_display_types.h"
#include "intel_dvo.h"
#include "intel_dvo_dev.h"
#include "intel_dvo_regs.h"
#include "intel_gmbus.h"
#include "intel_panel.h"

54
drivers/gpu/drm/i915/display/intel_dvo_regs.h Normal file
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@ -0,0 +1,54 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
#ifndef __INTEL_DVO_REGS_H__
#define __INTEL_DVO_REGS_H__
#include "intel_display_reg_defs.h"
#define _DVOA 0x61120
#define _DVOB 0x61140
#define _DVOC 0x61160
#define DVO(port) _MMIO_PORT((port), _DVOA, _DVOB)
#define DVO_ENABLE REG_BIT(31)
#define DVO_PIPE_SEL_MASK REG_BIT(30)
#define DVO_PIPE_SEL(pipe) REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
#define DVO_PIPE_STALL_MASK REG_GENMASK(29, 28)
#define DVO_PIPE_STALL_UNUSED REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
#define DVO_PIPE_STALL REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
#define DVO_PIPE_STALL_TV REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
#define DVO_INTERRUPT_SELECT REG_BIT(27)
#define DVO_DEDICATED_INT_ENABLE REG_BIT(26)
#define DVO_PRESERVE_MASK REG_GENMASK(25, 24)
#define DVO_USE_VGA_SYNC REG_BIT(15)
#define DVO_DATA_ORDER_MASK REG_BIT(14)
#define DVO_DATA_ORDER_I740 REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
#define DVO_DATA_ORDER_FP REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
#define DVO_VSYNC_DISABLE REG_BIT(11)
#define DVO_HSYNC_DISABLE REG_BIT(10)
#define DVO_VSYNC_TRISTATE REG_BIT(9)
#define DVO_HSYNC_TRISTATE REG_BIT(8)
#define DVO_BORDER_ENABLE REG_BIT(7)
#define DVO_ACT_DATA_ORDER_MASK REG_BIT(6)
#define DVO_ACT_DATA_ORDER_RGGB REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
#define DVO_ACT_DATA_ORDER_GBRG REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
#define DVO_ACT_DATA_ORDER_GBRG_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
#define DVO_ACT_DATA_ORDER_RGGB_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
#define DVO_VSYNC_ACTIVE_HIGH REG_BIT(4)
#define DVO_HSYNC_ACTIVE_HIGH REG_BIT(3)
#define DVO_BLANK_ACTIVE_HIGH REG_BIT(2)
#define DVO_OUTPUT_CSTATE_PIXELS REG_BIT(1) /* SDG only */
#define DVO_OUTPUT_SOURCE_SIZE_PIXELS REG_BIT(0) /* SDG only */
#define _DVOA_SRCDIM 0x61124
#define _DVOB_SRCDIM 0x61144
#define _DVOC_SRCDIM 0x61164
#define DVO_SRCDIM(port) _MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
#define DVO_SRCDIM_HORIZONTAL_MASK REG_GENMASK(22, 12)
#define DVO_SRCDIM_HORIZONTAL(x) REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))
#define DVO_SRCDIM_VERTICAL_MASK REG_GENMASK(10, 0)
#define DVO_SRCDIM_VERTICAL(x) REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))
#endif /* __INTEL_DVO_REGS_H__ */

44
drivers/gpu/drm/i915/i915_reg.h
View file

@ -2588,50 +2588,6 @@
#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
/* DVO port control */
#define _DVOA 0x61120
#define _DVOB 0x61140
#define _DVOC 0x61160
#define DVO(port) _MMIO_PORT((port), _DVOA, _DVOB)
#define DVO_ENABLE REG_BIT(31)
#define DVO_PIPE_SEL_MASK REG_BIT(30)
#define DVO_PIPE_SEL(pipe) REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
#define DVO_PIPE_STALL_MASK REG_GENMASK(29, 28)
#define DVO_PIPE_STALL_UNUSED REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
#define DVO_PIPE_STALL REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
#define DVO_PIPE_STALL_TV REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
#define DVO_INTERRUPT_SELECT REG_BIT(27)
#define DVO_DEDICATED_INT_ENABLE REG_BIT(26)
#define DVO_PRESERVE_MASK REG_GENMASK(25, 24)
#define DVO_USE_VGA_SYNC REG_BIT(15)
#define DVO_DATA_ORDER_MASK REG_BIT(14)
#define DVO_DATA_ORDER_I740 REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
#define DVO_DATA_ORDER_FP REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
#define DVO_VSYNC_DISABLE REG_BIT(11)
#define DVO_HSYNC_DISABLE REG_BIT(10)
#define DVO_VSYNC_TRISTATE REG_BIT(9)
#define DVO_HSYNC_TRISTATE REG_BIT(8)
#define DVO_BORDER_ENABLE REG_BIT(7)
#define DVO_ACT_DATA_ORDER_MASK REG_BIT(6)
#define DVO_ACT_DATA_ORDER_RGGB REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
#define DVO_ACT_DATA_ORDER_GBRG REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
#define DVO_ACT_DATA_ORDER_GBRG_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
#define DVO_ACT_DATA_ORDER_RGGB_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
#define DVO_VSYNC_ACTIVE_HIGH REG_BIT(4)
#define DVO_HSYNC_ACTIVE_HIGH REG_BIT(3)
#define DVO_BLANK_ACTIVE_HIGH REG_BIT(2)
#define DVO_OUTPUT_CSTATE_PIXELS REG_BIT(1) /* SDG only */
#define DVO_OUTPUT_SOURCE_SIZE_PIXELS REG_BIT(0) /* SDG only */
#define _DVOA_SRCDIM 0x61124
#define _DVOB_SRCDIM 0x61144
#define _DVOC_SRCDIM 0x61164
#define DVO_SRCDIM(port) _MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
#define DVO_SRCDIM_HORIZONTAL_MASK REG_GENMASK(22, 12)
#define DVO_SRCDIM_HORIZONTAL(x) REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))
#define DVO_SRCDIM_VERTICAL_MASK REG_GENMASK(10, 0)
#define DVO_SRCDIM_VERTICAL(x) REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))
/* LVDS port control */
#define LVDS _MMIO(0x61180)
/*