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drm/amdgpu/gfx7: enable cp/rlc ints after we disable clockgating
Even if we disable clockgating, we still need to make sure the cp/rlc interrupts are enabled for powergating which might still be enabled. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 7 additions and 4 deletions
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@ -3797,6 +3797,9 @@ static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
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gfx_v7_0_update_rlc(adev, tmp);
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data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
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if (orig != data)
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WREG32(mmRLC_CGCG_CGLS_CTRL, data);
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} else {
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gfx_v7_0_enable_gui_idle_interrupt(adev, false);
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@ -3806,11 +3809,11 @@ static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
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RREG32(mmCB_CGTT_SCLK_CTRL);
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data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
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if (orig != data)
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WREG32(mmRLC_CGCG_CGLS_CTRL, data);
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gfx_v7_0_enable_gui_idle_interrupt(adev, true);
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}
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if (orig != data)
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WREG32(mmRLC_CGCG_CGLS_CTRL, data);
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}
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static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
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