mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-30 06:10:56 +00:00
STM32 DT updates for v4.17, round 1
Highlights: ----------- -Add support of STM32MP157 MPU and stm32mp157c eval board -Add SD supports on F4 and F7 boards -Add leds support on stm32f469 and stm32f769 disco boards -Add push button support on stm32f469 and stm32f769 disco boards -Add EXTI, SPI, RTC, USB HS/FS support on STM32H743 MCU -Add RTC and USB OTG HS on stm32f769-disco -Use dedicated files for F7 pinctrl -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJanSS0AAoJEH+ayWryHnCFQEMP+wdYhe+zYC3fNNKksZOmTyIz fZJCaTbJhczZbpt5aaWJOIGIQC3Cf0UiSTGYV+XHa8bssZ+2WgnPfD0S6Qi2UTVH Eym5zIYSBtjzlovS4zk4XBPte41wjGSP3JeKh4s0zE/Qmmhkadb38nNPfT+KTRYX sq2o9yt0PreB6VLLRCEK5L5nesBPDL54dxeRRvHByp/Qg3qWgI4WjNpW7E8P65Ek 9HBPG97UbYlKj9M6aeepyiJSYK8ebGB/G+/IldNTgMautPsu3xmcP2VYia438/cI kc76/cm8AUNpJ98rbLMAZqeTqCbDKBnDzPiUXE8lsJaVknhpWhPpx//X1x4yt/+W O43mrwaRbfk5+61cRvyqNEqZhB8ECyQpDkqu5aBwn8zKqAtkTUqzkv87uDpaYgT3 1V1PFiAVqNmMKOBj4JMzyaJLuRkQX6xFoaF0J7luEknkzelwRVLkEeBHBh0irkDO yrpzKka+RA0cU7KKA9sMZSR4rU1i/tPjun1sVG05R5pplNWQLIj7Z5A/ZjeKEx+L sSaY9RWntGZ9+6n9a2SGHo/FOt3v8Fs7O7UszWs1fZMoxsSSI+v6UZcQyVlhkVwy 2ttp6eIFAOf7SaQdsrOEI0L9/DB6KR3LSfLu3Yt6XkLnxcDexghvFWp9ahPjCEmZ eX4T9gIZ/7S/Ampz3MRR =osrs -----END PGP SIGNATURE----- Merge tag 'stm32-dt-for-v4.17-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt Pull "STM32 DT updates for v4.17, round 1" from Alexandre Torgue: Highlights: ----------- -Add support of STM32MP157 MPU and stm32mp157c eval board -Add SD supports on F4 and F7 boards -Add leds support on stm32f469 and stm32f769 disco boards -Add push button support on stm32f469 and stm32f769 disco boards -Add EXTI, SPI, RTC, USB HS/FS support on STM32H743 MCU -Add RTC and USB OTG HS on stm32f769-disco -Use dedicated files for F7 pinctrl * tag 'stm32-dt-for-v4.17-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (34 commits) ARM: dts: stm32: Fix sdio2 rcc hard coded value dt-bindings: mfd: Add STM32F7 SDMMC2 rcc entry ARM: dts: stm32: Enable sdio1 for stm32f769-disco ARM: dts: stm32: Enable sdio1 for stm32f746-eval ARM: dts: stm32: Enable sdio1 for stm32f746-disco ARM: dts: stm32: Add sdio pins definition for stm32f7 ARM: dts: stm32: add SPI support on STM32H743 SoC ARM: dts: stm32: enable RTC on stm32h743i-eval ARM: dts: stm32: add RTC support on STM32H743 ARM: dts: stm32: enable USB OTG HS on stm32h743i-eval ARM: dts: stm32: add USB OTG HS and FS support for STM32H743 SoC ARM: dts: stm32: enable RTC on stm32f769-disco ARM: dts: stm32: enable USB HS on stm32f769-disco ARM: dts: stm32: select otg mode for usbotg_hs on stm32746g_eval ARM: dts: stm32: add gadget fifo sizes to usbotg_hs on stm32f746 ARM: dts: stm32: Add push button to stm32f769 Discovery board ARM: dts: stm32: Add push button to stm32f469 Discovery board ARM: dts: stm32: Add leds support to stm32f769 Discovery board ARM: dts: stm32: Add leds support to stm32f469 Discovery board ARM: dts: stm32: Fix HSE clock frequency for stm32h743i-disco board ...
This commit is contained in:
Arnd Bergmann
commit
dfbecbc7b6
23 changed files with 1165 additions and 223 deletions
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@ -7,3 +7,4 @@ using one of the following compatible strings:
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st,stm32f469
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st,stm32f746
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st,stm32h743
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st,stm32mp157
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@ -11,6 +11,7 @@ Required properies:
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"st,stm32f429-pinctrl"
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"st,stm32f469-pinctrl"
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"st,stm32f746-pinctrl"
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"st,stm32f769-pinctrl"
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"st,stm32h743-pinctrl"
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"st,stm32mp157-pinctrl"
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"st,stm32mp157-z-pinctrl"
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@ -866,7 +866,7 @@ dtb-$(CONFIG_ARCH_STI) += \
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stih410-b2120.dtb \
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stih410-b2260.dtb \
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stih418-b2199.dtb
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dtb-$(CONFIG_ARCH_STM32)+= \
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dtb-$(CONFIG_ARCH_STM32) += \
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stm32f429-disco.dtb \
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stm32f469-disco.dtb \
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stm32f746-disco.dtb \
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@ -874,7 +874,9 @@ dtb-$(CONFIG_ARCH_STM32)+= \
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stm32429i-eval.dtb \
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stm32746g-eval.dtb \
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stm32h743i-eval.dtb \
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stm32h743i-disco.dtb
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stm32h743i-disco.dtb \
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stm32mp157c-ed1.dtb \
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stm32mp157c-ev1.dtb
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dtb-$(CONFIG_MACH_SUN4I) += \
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sun4i-a10-a1000.dtb \
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sun4i-a10-ba10-tvbox.dtb \
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@ -144,6 +144,13 @@ panel_in_rgb: endpoint {
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};
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};
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};
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mmc_vcard: mmc_vcard {
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compatible = "regulator-fixed";
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regulator-name = "mmc_vcard";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&adc {
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@ -254,6 +261,18 @@ &rtc {
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status = "okay";
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};
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&sdio {
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status = "okay";
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vmmc-supply = <&mmc_vcard>;
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cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>;
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cd-inverted;
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pinctrl-names = "default", "opendrain";
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pinctrl-0 = <&sdio_pins>;
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pinctrl-1 = <&sdio_pins_od>;
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bus-width = <4>;
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max-frequency = <12500000>;
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};
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&timers1 {
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status = "okay";
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@ -42,6 +42,7 @@
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/dts-v1/;
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#include "stm32f746.dtsi"
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#include "stm32f746-pinctrl.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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@ -90,6 +91,13 @@ usbotg_hs_phy: usb-phy {
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
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clock-names = "main_clk";
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};
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mmc_vcard: mmc_vcard {
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compatible = "regulator-fixed";
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regulator-name = "mmc_vcard";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&clk_hse {
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@ -112,6 +120,16 @@ &rtc {
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status = "okay";
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};
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&sdio1 {
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status = "okay";
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vmmc-supply = <&mmc_vcard>;
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broken-cd;
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pinctrl-names = "default", "opendrain";
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pinctrl-0 = <&sdio_pins_a>;
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pinctrl-1 = <&sdio_pins_od_a>;
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bus-width = <4>;
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};
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&usart1 {
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pinctrl-0 = <&usart1_pins_a>;
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pinctrl-names = "default";
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@ -119,7 +137,7 @@ &usart1 {
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};
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&usbotg_hs {
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dr_mode = "host";
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dr_mode = "otg";
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phys = <&usbotg_hs_phy>;
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phy-names = "usb2-phy";
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pinctrl-0 = <&usbotg_hs_pins_a>;
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@ -338,6 +338,37 @@ pins {
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slew-rate = <3>;
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};
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};
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sdio_pins: sdio_pins@0 {
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pins {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
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<STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
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<STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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sdio_pins_od: sdio_pins_od@0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
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<STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
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drive-open-drain;
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slew-rate = <2>;
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};
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};
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};
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};
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};
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@ -511,6 +511,17 @@ adc3: adc@200 {
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};
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};
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sdio: sdio@40012c00 {
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compatible = "arm,pl180", "arm,primecell";
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arm,primecell-periphid = <0x00880180>;
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reg = <0x40012c00 0x400>;
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clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
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clock-names = "apb_pclk";
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interrupts = <49>;
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max-frequency = <48000000>;
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status = "disabled";
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};
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syscfg: system-config@40013800 {
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compatible = "syscon";
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reg = <0x40013800 0x400>;
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@ -48,6 +48,8 @@
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/dts-v1/;
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#include "stm32f429.dtsi"
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#include "stm32f469-pinctrl.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "STMicroelectronics STM32F469i-DISCO board";
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@ -66,10 +68,46 @@ aliases {
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serial0 = &usart3;
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};
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mmc_vcard: mmc_vcard {
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compatible = "regulator-fixed";
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regulator-name = "mmc_vcard";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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soc {
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dma-ranges = <0xc0000000 0x0 0x10000000>;
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};
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leds {
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compatible = "gpio-leds";
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green {
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gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "heartbeat";
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};
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orange {
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gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
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};
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red {
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gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
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};
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blue {
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gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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autorepeat;
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button@0 {
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label = "User";
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linux,code = <KEY_WAKEUP>;
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gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
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};
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};
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/* This turns on vbus for otg for host mode (dwc2) */
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vcc5v_otg: vcc5v-otg-regulator {
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compatible = "regulator-fixed";
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@ -120,6 +158,18 @@ timer@2 {
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};
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};
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&sdio {
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status = "okay";
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vmmc-supply = <&mmc_vcard>;
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cd-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
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cd-inverted;
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broken-cd;
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pinctrl-names = "default", "opendrain";
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pinctrl-0 = <&sdio_pins>;
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pinctrl-1 = <&sdio_pins_od>;
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bus-width = <4>;
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};
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&usart3 {
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pinctrl-0 = <&usart3_pins_a>;
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pinctrl-names = "default";
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289
arch/arm/boot/dts/stm32f7-pinctrl.dtsi
Normal file
289
arch/arm/boot/dts/stm32f7-pinctrl.dtsi
Normal file
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@ -0,0 +1,289 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <dt-bindings/mfd/stm32f7-rcc.h>
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/ {
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soc {
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pinctrl: pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x40020000 0x3000>;
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interrupt-parent = <&exti>;
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st,syscfg = <&syscfg 0x8>;
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pins-are-numbered;
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gpioa: gpio@40020000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
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st,bank-name = "GPIOA";
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};
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gpiob: gpio@40020400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x400 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
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st,bank-name = "GPIOB";
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};
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gpioc: gpio@40020800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x800 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
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st,bank-name = "GPIOC";
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};
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gpiod: gpio@40020c00 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xc00 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
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st,bank-name = "GPIOD";
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};
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gpioe: gpio@40021000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
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st,bank-name = "GPIOE";
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};
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gpiof: gpio@40021400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1400 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
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st,bank-name = "GPIOF";
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};
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gpiog: gpio@40021800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
|
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#interrupt-cells = <2>;
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reg = <0x1800 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
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st,bank-name = "GPIOG";
|
||||
};
|
||||
|
||||
gpioh: gpio@40021c00 {
|
||||
gpio-controller;
|
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#gpio-cells = <2>;
|
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interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1c00 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
|
||||
st,bank-name = "GPIOH";
|
||||
};
|
||||
|
||||
gpioi: gpio@40022000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
|
||||
st,bank-name = "GPIOI";
|
||||
};
|
||||
|
||||
gpioj: gpio@40022400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2400 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
|
||||
st,bank-name = "GPIOJ";
|
||||
};
|
||||
|
||||
gpiok: gpio@40022800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2800 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
|
||||
st,bank-name = "GPIOK";
|
||||
};
|
||||
|
||||
cec_pins_a: cec@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
|
||||
slew-rate = <0>;
|
||||
drive-open-drain;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins_a: usart1@0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins_b: usart1@1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_b: i2c1@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
|
||||
<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_pins_a: usbotg-hs@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
|
||||
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
|
||||
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
|
||||
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
|
||||
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
|
||||
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
|
||||
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
|
||||
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
|
||||
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
|
||||
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
|
||||
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
|
||||
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_pins_b: usbotg-hs@1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
|
||||
<STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
|
||||
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
|
||||
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
|
||||
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
|
||||
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
|
||||
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
|
||||
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
|
||||
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
|
||||
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
|
||||
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
|
||||
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_fs_pins_a: usbotg-fs@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
|
||||
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
|
||||
<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pins_a: sdio_pins_a@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
|
||||
<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
|
||||
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pins_od_a: sdio_pins_od_a@0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
|
||||
<STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
|
||||
drive-open-drain;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pins_b: sdio_pins_b@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
|
||||
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
|
||||
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
|
||||
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
|
||||
<STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
|
||||
<STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pins_od_b: sdio_pins_od_b@0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
|
||||
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
|
||||
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
|
||||
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
|
||||
<STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
|
||||
drive-open-drain;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -42,7 +42,9 @@
|
|||
|
||||
/dts-v1/;
|
||||
#include "stm32f746.dtsi"
|
||||
#include "stm32f746-pinctrl.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32F746-DISCO board";
|
||||
|
|
@ -75,12 +77,30 @@ vcc5v_otg_fs: vcc5v-otg-fs-regulator {
|
|||
regulator-name = "vcc5_host1";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mmc_vcard: mmc_vcard {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "mmc_vcard";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&sdio1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&mmc_vcard>;
|
||||
cd-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
|
||||
cd-inverted;
|
||||
pinctrl-names = "default", "opendrain";
|
||||
pinctrl-0 = <&sdio_pins_a>;
|
||||
pinctrl-1 = <&sdio_pins_od_a>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-0 = <&usart1_pins_b>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
11
arch/arm/boot/dts/stm32f746-pinctrl.dtsi
Normal file
11
arch/arm/boot/dts/stm32f746-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32f7-pinctrl.dtsi"
|
||||
|
||||
&pinctrl{
|
||||
compatible = "st,stm32f746-pinctrl";
|
||||
};
|
||||
|
|
@ -42,7 +42,6 @@
|
|||
|
||||
#include "skeleton.dtsi"
|
||||
#include "armv7-m.dtsi"
|
||||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
#include <dt-bindings/clock/stm32fx-clock.h>
|
||||
#include <dt-bindings/mfd/stm32f7-rcc.h>
|
||||
|
||||
|
|
@ -429,6 +428,28 @@ usart6: serial@40011400 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio2: sdio2@40011c00 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00880180>;
|
||||
reg = <0x40011c00 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
|
||||
clock-names = "apb_pclk";
|
||||
interrupts = <103>;
|
||||
max-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio1: sdio1@40012c00 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00880180>;
|
||||
reg = <0x40012c00 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
|
||||
clock-names = "apb_pclk";
|
||||
interrupts = <49>;
|
||||
max-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
syscfg: system-config@40013800 {
|
||||
compatible = "syscon";
|
||||
reg = <0x40013800 0x400>;
|
||||
|
|
@ -498,222 +519,6 @@ pwrcfg: power-config@40007000 {
|
|||
reg = <0x40007000 0x400>;
|
||||
};
|
||||
|
||||
pin-controller {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32f746-pinctrl";
|
||||
ranges = <0 0x40020000 0x3000>;
|
||||
interrupt-parent = <&exti>;
|
||||
st,syscfg = <&syscfg 0x8>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@40020000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
|
||||
st,bank-name = "GPIOA";
|
||||
};
|
||||
|
||||
gpiob: gpio@40020400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x400 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
|
||||
st,bank-name = "GPIOB";
|
||||
};
|
||||
|
||||
gpioc: gpio@40020800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x800 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
|
||||
st,bank-name = "GPIOC";
|
||||
};
|
||||
|
||||
gpiod: gpio@40020c00 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xc00 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
|
||||
st,bank-name = "GPIOD";
|
||||
};
|
||||
|
||||
gpioe: gpio@40021000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
|
||||
st,bank-name = "GPIOE";
|
||||
};
|
||||
|
||||
gpiof: gpio@40021400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1400 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
|
||||
st,bank-name = "GPIOF";
|
||||
};
|
||||
|
||||
gpiog: gpio@40021800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1800 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
|
||||
st,bank-name = "GPIOG";
|
||||
};
|
||||
|
||||
gpioh: gpio@40021c00 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1c00 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
|
||||
st,bank-name = "GPIOH";
|
||||
};
|
||||
|
||||
gpioi: gpio@40022000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
|
||||
st,bank-name = "GPIOI";
|
||||
};
|
||||
|
||||
gpioj: gpio@40022400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2400 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
|
||||
st,bank-name = "GPIOJ";
|
||||
};
|
||||
|
||||
gpiok: gpio@40022800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2800 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
|
||||
st,bank-name = "GPIOK";
|
||||
};
|
||||
|
||||
cec_pins_a: cec@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
|
||||
slew-rate = <0>;
|
||||
drive-open-drain;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins_a: usart1@0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins_b: usart1@1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_b: i2c1@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
|
||||
<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_pins_a: usbotg-hs@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
|
||||
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
|
||||
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
|
||||
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
|
||||
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
|
||||
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
|
||||
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
|
||||
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
|
||||
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
|
||||
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
|
||||
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
|
||||
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_pins_b: usbotg-hs@1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
|
||||
<STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
|
||||
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
|
||||
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
|
||||
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
|
||||
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
|
||||
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
|
||||
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
|
||||
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
|
||||
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
|
||||
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
|
||||
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_fs_pins_a: usbotg-fs@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
|
||||
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
|
||||
<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
crc: crc@40023000 {
|
||||
compatible = "st,stm32f7-crc";
|
||||
reg = <0x40023000 0x400>;
|
||||
|
|
@ -771,6 +576,9 @@ usbotg_hs: usb@40040000 {
|
|||
interrupts = <77>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
|
||||
clock-names = "otg";
|
||||
g-rx-fifo-size = <256>;
|
||||
g-np-tx-fifo-size = <32>;
|
||||
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -42,11 +42,13 @@
|
|||
|
||||
/dts-v1/;
|
||||
#include "stm32f746.dtsi"
|
||||
#include "stm32f769-pinctrl.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32F769-DISCO board";
|
||||
compatible = "st,stm32f769-disco", "st,stm32f7";
|
||||
compatible = "st,stm32f769-disco", "st,stm32f769";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram";
|
||||
|
|
@ -61,6 +63,42 @@ aliases {
|
|||
serial0 = &usart1;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
green {
|
||||
gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
red {
|
||||
gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
button@0 {
|
||||
label = "User";
|
||||
linux,code = <KEY_HOME>;
|
||||
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_phy: usb-phy {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
mmc_vcard: mmc_vcard {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "mmc_vcard";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cec {
|
||||
|
|
@ -73,8 +111,33 @@ &clk_hse {
|
|||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio2 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&mmc_vcard>;
|
||||
cd-gpios = <&gpioi 15 GPIO_ACTIVE_HIGH>;
|
||||
cd-inverted;
|
||||
broken-cd;
|
||||
pinctrl-names = "default", "opendrain";
|
||||
pinctrl-0 = <&sdio_pins_b>;
|
||||
pinctrl-1 = <&sdio_pins_od_b>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-0 = <&usart1_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
dr_mode = "otg";
|
||||
phys = <&usbotg_hs_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
pinctrl-0 = <&usbotg_hs_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
11
arch/arm/boot/dts/stm32f769-pinctrl.dtsi
Normal file
11
arch/arm/boot/dts/stm32f769-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32f7-pinctrl.dtsi"
|
||||
|
||||
&pinctrl{
|
||||
compatible = "st,stm32f769-pinctrl";
|
||||
};
|
||||
|
|
@ -49,6 +49,8 @@ pin-controller {
|
|||
#size-cells = <1>;
|
||||
compatible = "st,stm32h743-pinctrl";
|
||||
ranges = <0 0x58020000 0x3000>;
|
||||
interrupt-parent = <&exti>;
|
||||
st,syscfg = <&syscfg 0x8>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@58020000 {
|
||||
|
|
@ -57,6 +59,8 @@ gpioa: gpio@58020000 {
|
|||
reg = <0x0 0x400>;
|
||||
clocks = <&rcc GPIOA_CK>;
|
||||
st,bank-name = "GPIOA";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpiob: gpio@58020400 {
|
||||
|
|
@ -65,6 +69,8 @@ gpiob: gpio@58020400 {
|
|||
reg = <0x400 0x400>;
|
||||
clocks = <&rcc GPIOB_CK>;
|
||||
st,bank-name = "GPIOB";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpioc: gpio@58020800 {
|
||||
|
|
@ -73,6 +79,8 @@ gpioc: gpio@58020800 {
|
|||
reg = <0x800 0x400>;
|
||||
clocks = <&rcc GPIOC_CK>;
|
||||
st,bank-name = "GPIOC";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpiod: gpio@58020c00 {
|
||||
|
|
@ -81,6 +89,8 @@ gpiod: gpio@58020c00 {
|
|||
reg = <0xc00 0x400>;
|
||||
clocks = <&rcc GPIOD_CK>;
|
||||
st,bank-name = "GPIOD";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpioe: gpio@58021000 {
|
||||
|
|
@ -89,6 +99,8 @@ gpioe: gpio@58021000 {
|
|||
reg = <0x1000 0x400>;
|
||||
clocks = <&rcc GPIOE_CK>;
|
||||
st,bank-name = "GPIOE";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpiof: gpio@58021400 {
|
||||
|
|
@ -97,6 +109,8 @@ gpiof: gpio@58021400 {
|
|||
reg = <0x1400 0x400>;
|
||||
clocks = <&rcc GPIOF_CK>;
|
||||
st,bank-name = "GPIOF";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpiog: gpio@58021800 {
|
||||
|
|
@ -105,6 +119,8 @@ gpiog: gpio@58021800 {
|
|||
reg = <0x1800 0x400>;
|
||||
clocks = <&rcc GPIOG_CK>;
|
||||
st,bank-name = "GPIOG";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpioh: gpio@58021c00 {
|
||||
|
|
@ -113,6 +129,8 @@ gpioh: gpio@58021c00 {
|
|||
reg = <0x1c00 0x400>;
|
||||
clocks = <&rcc GPIOH_CK>;
|
||||
st,bank-name = "GPIOH";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpioi: gpio@58022000 {
|
||||
|
|
@ -121,6 +139,8 @@ gpioi: gpio@58022000 {
|
|||
reg = <0x2000 0x400>;
|
||||
clocks = <&rcc GPIOI_CK>;
|
||||
st,bank-name = "GPIOI";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpioj: gpio@58022400 {
|
||||
|
|
@ -129,6 +149,8 @@ gpioj: gpio@58022400 {
|
|||
reg = <0x2400 0x400>;
|
||||
clocks = <&rcc GPIOJ_CK>;
|
||||
st,bank-name = "GPIOJ";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpiok: gpio@58022800 {
|
||||
|
|
@ -137,6 +159,8 @@ gpiok: gpio@58022800 {
|
|||
reg = <0x2800 0x400>;
|
||||
clocks = <&rcc GPIOK_CK>;
|
||||
st,bank-name = "GPIOK";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
usart1_pins: usart1@0 {
|
||||
|
|
@ -164,6 +188,26 @@ pins2 {
|
|||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_pins_a: usbotg-hs@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
|
||||
<STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
|
||||
<STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
|
||||
<STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
|
||||
<STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
|
||||
<STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
|
||||
<STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
|
||||
<STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
|
||||
<STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
|
||||
<STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
|
||||
<STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
|
||||
<STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@
|
|||
#include "armv7-m.dtsi"
|
||||
#include <dt-bindings/clock/stm32h7-clks.h>
|
||||
#include <dt-bindings/mfd/stm32h7-rcc.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
|
|
@ -100,6 +101,27 @@ counter {
|
|||
};
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x40003800 0x400>;
|
||||
interrupts = <36>;
|
||||
clocks = <&rcc SPI2_CK>;
|
||||
status = "disabled";
|
||||
|
||||
};
|
||||
|
||||
spi3: spi@40003c00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x40003c00 0x400>;
|
||||
interrupts = <51>;
|
||||
clocks = <&rcc SPI3_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@40004400 {
|
||||
compatible = "st,stm32f7-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
|
|
@ -140,6 +162,36 @@ usart1: serial@40011000 {
|
|||
clocks = <&rcc USART1_CK>;
|
||||
};
|
||||
|
||||
spi1: spi@40013000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x40013000 0x400>;
|
||||
interrupts = <35>;
|
||||
clocks = <&rcc SPI1_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@40013400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x40013400 0x400>;
|
||||
interrupts = <84>;
|
||||
clocks = <&rcc SPI4_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi5: spi@40015000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x40015000 0x400>;
|
||||
interrupts = <85>;
|
||||
clocks = <&rcc SPI5_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma1: dma@40020000 {
|
||||
compatible = "st,stm32-dma";
|
||||
reg = <0x40020000 0x400>;
|
||||
|
|
@ -217,6 +269,27 @@ adc2: adc@100 {
|
|||
};
|
||||
};
|
||||
|
||||
usbotg_hs: usb@40040000 {
|
||||
compatible = "st,stm32f7-hsotg";
|
||||
reg = <0x40040000 0x40000>;
|
||||
interrupts = <77>;
|
||||
clocks = <&rcc USB1OTG_CK>;
|
||||
clock-names = "otg";
|
||||
g-rx-fifo-size = <256>;
|
||||
g-np-tx-fifo-size = <32>;
|
||||
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg_fs: usb@40080000 {
|
||||
compatible = "st,stm32f4x9-fsotg";
|
||||
reg = <0x40080000 0x40000>;
|
||||
interrupts = <101>;
|
||||
clocks = <&rcc USB2OTG_CK>;
|
||||
clock-names = "otg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdma1: dma@52000000 {
|
||||
compatible = "st,stm32h7-mdma";
|
||||
reg = <0x52000000 0x1000>;
|
||||
|
|
@ -227,6 +300,29 @@ mdma1: dma@52000000 {
|
|||
dma-requests = <32>;
|
||||
};
|
||||
|
||||
exti: interrupt-controller@58000000 {
|
||||
compatible = "st,stm32h7-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x58000000 0x400>;
|
||||
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
|
||||
};
|
||||
|
||||
syscfg: system-config@58000400 {
|
||||
compatible = "syscon";
|
||||
reg = <0x58000400 0x400>;
|
||||
};
|
||||
|
||||
spi6: spi@58001400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x58001400 0x400>;
|
||||
interrupts = <86>;
|
||||
clocks = <&rcc SPI6_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lptimer2: timer@58002400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -304,7 +400,7 @@ pwm {
|
|||
};
|
||||
};
|
||||
|
||||
vrefbuf: regulator@58003C00 {
|
||||
vrefbuf: regulator@58003c00 {
|
||||
compatible = "st,stm32-vrefbuf";
|
||||
reg = <0x58003C00 0x8>;
|
||||
clocks = <&rcc VREF_CK>;
|
||||
|
|
@ -313,6 +409,20 @@ vrefbuf: regulator@58003C00 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@58004000 {
|
||||
compatible = "st,stm32h7-rtc";
|
||||
reg = <0x58004000 0x400>;
|
||||
clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
|
||||
clock-names = "pclk", "rtc_ck";
|
||||
assigned-clocks = <&rcc RTC_CK>;
|
||||
assigned-clock-parents = <&rcc LSE_CK>;
|
||||
interrupt-parent = <&exti>;
|
||||
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "alarm";
|
||||
st,syscfg = <&pwrcfg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcc: reset-clock-controller@58024400 {
|
||||
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
|
||||
reg = <0x58024400 0x400>;
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ aliases {
|
|||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <125000000>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
|
|
|
|||
|
|
@ -68,6 +68,14 @@ vdda: regulator-vdda {
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
usbotg_hs_phy: usb-phy {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&rcc USB1ULPI_CK>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&adc_12 {
|
||||
|
|
@ -84,9 +92,21 @@ &clk_hse {
|
|||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-0 = <&usart1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
pinctrl-0 = <&usbotg_hs_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
phys = <&usbotg_hs_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
185
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
Normal file
185
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,185 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp157-pinctrl";
|
||||
ranges = <0 0x50002000 0xa400>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
st,bank-name = "GPIOA";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
st,bank-name = "GPIOB";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
st,bank-name = "GPIOC";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x3000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
st,bank-name = "GPIOD";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
st,bank-name = "GPIOE";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
st,bank-name = "GPIOF";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x6000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
st,bank-name = "GPIOG";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x7000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
st,bank-name = "GPIOH";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x8000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
st,bank-name = "GPIOI";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@5000b000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x9000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
st,bank-name = "GPIOJ";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@5000c000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xa000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
st,bank-name = "GPIOK";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
|
||||
uart4_pins_a: uart4@0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp157-z-pinctrl";
|
||||
ranges = <0 0x54004000 0x400>;
|
||||
pins-are-numbered;
|
||||
status = "disabled";
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x400>;
|
||||
clocks = <&clk_pll2_p>;
|
||||
st,bank-name = "GPIOZ";
|
||||
st,bank-ioport = <11>;
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
32
arch/arm/boot/dts/stm32mp157c-ed1.dts
Normal file
32
arch/arm/boot/dts/stm32mp157c-ed1.dts
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c.dtsi"
|
||||
#include "stm32mp157-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C eval daughter";
|
||||
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0xC0000000 0x40000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
21
arch/arm/boot/dts/stm32mp157c-ev1.dts
Normal file
21
arch/arm/boot/dts/stm32mp157c-ev1.dts
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c-ed1.dts"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
|
||||
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
};
|
||||
};
|
||||
194
arch/arm/boot/dts/stm32mp157c.dtsi
Normal file
194
arch/arm/boot/dts/stm32mp157c.dtsi
Normal file
|
|
@ -0,0 +1,194 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a7";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a7";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci";
|
||||
method = "smc";
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_on = <0x84000003>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpioa;
|
||||
gpio1 = &gpiob;
|
||||
gpio2 = &gpioc;
|
||||
gpio3 = &gpiod;
|
||||
gpio4 = &gpioe;
|
||||
gpio5 = &gpiof;
|
||||
gpio6 = &gpiog;
|
||||
gpio7 = &gpioh;
|
||||
gpio8 = &gpioi;
|
||||
gpio9 = &gpioj;
|
||||
gpio10 = &gpiok;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@a0021000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xa0021000 0x1000>,
|
||||
<0xa0022000 0x2000>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
clk_pll_per: clk-pll-per {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <64000000>;
|
||||
};
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <64000000>;
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_lsi: clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
clk_csi: clk-csi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <4000000>;
|
||||
};
|
||||
|
||||
clk_pclk1: clk-pclk1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <86000000>;
|
||||
};
|
||||
|
||||
clk_pll3_p: clk-pll3_p {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <172000000>;
|
||||
};
|
||||
|
||||
clk_pll2_p: clk-pll2_p {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <264000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
usart2: serial@4000e000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x4000e000 0x400>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@4000f000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x4000f000 0x400>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@40010000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40010000 0x400>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@40011000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40011000 0x400>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: serial@40018000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40018000 0x400>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart8: serial@40019000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40019000 0x400>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart6: serial@44003000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x44003000 0x400>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@5c000000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x5c000000 0x400>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -91,6 +91,7 @@
|
|||
#define STM32F7_RCC_APB2_TIM8 1
|
||||
#define STM32F7_RCC_APB2_USART1 4
|
||||
#define STM32F7_RCC_APB2_USART6 5
|
||||
#define STM32F7_RCC_APB2_SDMMC2 7
|
||||
#define STM32F7_RCC_APB2_ADC1 8
|
||||
#define STM32F7_RCC_APB2_ADC2 9
|
||||
#define STM32F7_RCC_APB2_ADC3 10
|
||||
|
|
|
|||
Loading…
Reference in a new issue