mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-06 08:46:46 +00:00
Merge branches 'clk-renesas', 'clk-spreadtrum', 'clk-imx' and 'clk-qcom' into clk-next
* clk-renesas: (22 commits) clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_config clk: renesas: r9a07g043: Add support for RZ/Five SoC dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions clk: renesas: r8a779f0: Add HSCIF clocks clk: renesas: r8a779f0: Add PCIe clocks clk: renesas: r8a779f0: Add Z0 and Z1 clock support dt-bindings: clock: renesas,rzg2l: Simplify header file references clk: renesas: rza1: Remove struct rz_cpg clk: renesas: r8a7779: Remove struct r8a7779_cpg clk: renesas: r8a7778: Remove struct r8a7778_cpg clk: renesas: sh73a0: Remove sh73a0_cpg.reg clk: renesas: r8a7740: Remove r8a7740_cpg.reg clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg clk: renesas: r8a779f0: Add SDHI0 clock clk: renesas: r8a779f0: Add thermal clock clk: renesas: rzg2l: Fix reset status function clk: renesas: r9a06g032: Fix UART clkgrp bitsel clk: renesas: r9a06g032: Drop some unused fields clk: renesas: r9a09g011: Add WDT clock and reset entries clk: renesas: r9a09g011: Add PFC clock and reset entries ... * clk-spreadtrum: clk: sprd: Add dt-bindings include file for UMS512 dt-bindings: clk: sprd: Add bindings for ums512 clock controller * clk-imx: clk: imx: clk-fracn-gppll: Add more freq config for video pll clk: imx: clk-fracn-gppll: correct rdiv clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate() clk: imx: clk-fracn-gppll: fix mfd value clk: imx93: Correct the edma1's parent clock clk: imx93: correct nic_media parent clk: imx93: use adc_root as the parent clock of adc1 * clk-qcom: (62 commits) clk: qcom: gcc-msm8994: use parent_hws for gpll0/4 clk: qcom: clk-rpm: convert to parent_data API dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled clk: qcom: Drop mmcx gdsc supply for dispcc and videocc clk: qcom: fix build error initializer element is not constant dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources clk: qcom: add support for SM8350 DISPCC clk: qcom: add support for SM8350 GPUCC clk: qcom: add camera clock controller driver for SM8450 SoC clk: qcom: clk-alpha-pll: add Rivian EVO PLL configuration interfaces clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces clk: qcom: clk-alpha-pll: limit exported symbols to GPL licensed code clk: qcom: clk-alpha-pll: fix clk_trion_pll_configure description ...
This commit is contained in:
Stephen Boyd
commit
dfcbbd73dd
64 changed files with 6030 additions and 777 deletions
|
|
@ -4,18 +4,19 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
|
||||
|
||||
maintainers:
|
||||
- Jonathan Marek <jonathan@marek.ca>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SM8150 and SM8250.
|
||||
power domains on SM8150/SM8250/SM8350.
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/qcom,dispcc-sm8150.h
|
||||
dt-bindings/clock/qcom,dispcc-sm8250.h
|
||||
dt-bindings/clock/qcom,dispcc-sm8350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -23,6 +24,7 @@ properties:
|
|||
- qcom,sc8180x-dispcc
|
||||
- qcom,sm8150-dispcc
|
||||
- qcom,sm8250-dispcc
|
||||
- qcom,sm8350-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064/MSM8960
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
@ -23,11 +23,25 @@ description: |
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-apq8064
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,gcc-apq8064
|
||||
- qcom,gcc-msm8960
|
||||
- const: syscon
|
||||
- enum:
|
||||
- qcom,gcc-apq8064
|
||||
- qcom,gcc-msm8960
|
||||
deprecated: true
|
||||
|
||||
thermal-sensor:
|
||||
description: child tsens device
|
||||
$ref: /schemas/thermal/qcom-tsens.yaml#
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
deprecated: true
|
||||
description:
|
||||
Qualcomm TSENS (thermal sensor device) on some devices can
|
||||
be part of GCC and hence the TSENS properties can also be part
|
||||
|
|
@ -37,31 +51,39 @@ properties:
|
|||
|
||||
nvmem-cell-names:
|
||||
minItems: 1
|
||||
deprecated: true
|
||||
items:
|
||||
- const: calib
|
||||
- const: calib_backup
|
||||
|
||||
'#thermal-sensor-cells':
|
||||
const: 1
|
||||
deprecated: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- nvmem-cells
|
||||
- nvmem-cell-names
|
||||
- '#thermal-sensor-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-apq8064";
|
||||
compatible = "qcom,gcc-apq8064", "syscon";
|
||||
reg = <0x00900000 0x4000>;
|
||||
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
nvmem-cell-names = "calib", "calib_backup";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
|
||||
thermal-sensor {
|
||||
compatible = "qcom,msm8960-tsens";
|
||||
|
||||
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
nvmem-cell-names = "calib", "calib_backup";
|
||||
interrupts = <0 178 4>;
|
||||
interrupt-names = "uplow";
|
||||
|
||||
#qcom,sensors = <11>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -24,6 +24,9 @@ properties:
|
|||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
|
|
@ -38,6 +41,7 @@ required:
|
|||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -48,6 +52,7 @@ examples:
|
|||
compatible = "qcom,gcc-ipq8074";
|
||||
reg = <0x01800000 0x80000>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -22,16 +22,32 @@ properties:
|
|||
const: qcom,gcc-msm8996
|
||||
|
||||
clocks:
|
||||
minItems: 3
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Second XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIe 0 PIPE clock (optional)
|
||||
- description: PCIe 1 PIPE clock (optional)
|
||||
- description: PCIe 2 PIPE clock (optional)
|
||||
- description: USB3 PIPE clock (optional)
|
||||
- description: UFS RX symbol 0 clock (optional)
|
||||
- description: UFS RX symbol 1 clock (optional)
|
||||
- description: UFS TX symbol 0 clock (optional)
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
items:
|
||||
- const: cxo
|
||||
- const: cxo2
|
||||
- const: sleep_clk
|
||||
- const: pcie_0_pipe_clk_src
|
||||
- const: pcie_1_pipe_clk_src
|
||||
- const: pcie_2_pipe_clk_src
|
||||
- const: usb3_phy_pipe_clk_src
|
||||
- const: ufs_rx_symbol_0_clk_src
|
||||
- const: ufs_rx_symbol_1_clk_src
|
||||
- const: ufs_tx_symbol_0_clk_src
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
|
|
|||
|
|
@ -44,7 +44,6 @@ properties:
|
|||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8939
|
||||
- qcom,gcc-msm8953
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
|
|
@ -58,10 +57,10 @@ required:
|
|||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8960:
|
||||
# Example for GCC for MSM8974:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960";
|
||||
compatible = "qcom,gcc-msm8974";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -43,6 +43,9 @@ properties:
|
|||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,72 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding
|
||||
|
||||
maintainers:
|
||||
- Robert Foss <robert.foss@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on Qualcomm SoCs.
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/qcom,gpucc-sm8350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8350-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@3d90000 {
|
||||
compatible = "qcom,sm8350-gpucc";
|
||||
reg = <0 0x03d90000 0 0x9000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -49,15 +49,86 @@ properties:
|
|||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
const: xo
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,rpmcc-apq8060
|
||||
- qcom,rpmcc-ipq806x
|
||||
- qcom,rpmcc-msm8660
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: pxo clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pxo
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,rpmcc-apq8064
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: pxo clock
|
||||
- description: cxo clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pxo
|
||||
- const: cxo
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,rpmcc-mdm9607
|
||||
- qcom,rpmcc-msm8226
|
||||
- qcom,rpmcc-msm8916
|
||||
- qcom,rpmcc-msm8936
|
||||
- qcom,rpmcc-msm8953
|
||||
- qcom,rpmcc-msm8974
|
||||
- qcom,rpmcc-msm8976
|
||||
- qcom,rpmcc-msm8992
|
||||
- qcom,rpmcc-msm8994
|
||||
- qcom,rpmcc-msm8996
|
||||
- qcom,rpmcc-msm8998
|
||||
- qcom,rpmcc-qcm2290
|
||||
- qcom,rpmcc-qcs404
|
||||
- qcom,rpmcc-sdm660
|
||||
- qcom,rpmcc-sm6115
|
||||
- qcom,rpmcc-sm6125
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: xo clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -73,3 +144,13 @@ examples:
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
rpm {
|
||||
clock-controller {
|
||||
compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&pxo_board>;
|
||||
clock-names = "pxo";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,80 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller Binding for SM8450
|
||||
|
||||
maintainers:
|
||||
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module which supports the clocks, resets and
|
||||
power domains on SM8450.
|
||||
|
||||
See also include/dt-bindings/clock/qcom,sm8450-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8450-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Camera AHB clock from GCC
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
clock-controller@ade0000 {
|
||||
compatible = "qcom,sm8450-camcc";
|
||||
reg = <0xade0000 0x20000>;
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
power-domains = <&rpmhpd SM8450_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -45,10 +45,9 @@ properties:
|
|||
description: |
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/r9a0*-cpg.h>
|
||||
<dt-bindings/clock/r9a0*-cpg.h>,
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
|
||||
<dt-bindings/clock/r9a09g011-cpg.h>.
|
||||
a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
|
||||
const: 2
|
||||
|
||||
'#power-domain-cells':
|
||||
|
|
@ -62,7 +61,7 @@ properties:
|
|||
'#reset-cells':
|
||||
description:
|
||||
The single reset specifier cell must be the module number, as defined in
|
||||
the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
|
||||
<dt-bindings/clock/r9a0*-cpg.h>.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
|
|
|
|||
71
Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
Normal file
71
Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright 2022 Unisoc Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: UMS512 Soc clock controller
|
||||
|
||||
maintainers:
|
||||
- Orson Zhai <orsonzhai@gmail.com>
|
||||
- Baolin Wang <baolin.wang7@gmail.com>
|
||||
- Chunyan Zhang <zhang.lyra@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- sprd,ums512-apahb-gate
|
||||
- sprd,ums512-ap-clk
|
||||
- sprd,ums512-aonapb-clk
|
||||
- sprd,ums512-pmu-gate
|
||||
- sprd,ums512-g0-pll
|
||||
- sprd,ums512-g2-pll
|
||||
- sprd,ums512-g3-pll
|
||||
- sprd,ums512-gc-pll
|
||||
- sprd,ums512-aon-gate
|
||||
- sprd,ums512-audcpapb-gate
|
||||
- sprd,ums512-audcpahb-gate
|
||||
- sprd,ums512-gpu-clk
|
||||
- sprd,ums512-mm-clk
|
||||
- sprd,ums512-mm-gate-clk
|
||||
- sprd,ums512-apapb-gate
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
description: |
|
||||
The input parent clock(s) phandle for the clock, only list
|
||||
fixed clocks which are declared in devicetree.
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: ext-26m
|
||||
- const: ext-32k
|
||||
- const: ext-4m
|
||||
- const: rco-100m
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ap_clk: clock-controller@20200000 {
|
||||
compatible = "sprd,ums512-ap-clk";
|
||||
reg = <0x20200000 0x1000>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "ext-26m";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -64,10 +64,13 @@ struct clk_fracn_gppll {
|
|||
* Fout = Fvco / (rdiv * odiv)
|
||||
*/
|
||||
static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
|
||||
PLL_FRACN_GP(650000000U, 81, 0, 0, 0, 3),
|
||||
PLL_FRACN_GP(594000000U, 198, 0, 0, 0, 8),
|
||||
PLL_FRACN_GP(560000000U, 70, 0, 0, 0, 3),
|
||||
PLL_FRACN_GP(400000000U, 50, 0, 0, 0, 3),
|
||||
PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3),
|
||||
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
|
||||
PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3),
|
||||
PLL_FRACN_GP(498000000U, 83, 0, 1, 0, 4),
|
||||
PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
|
||||
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
|
||||
PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3),
|
||||
PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5)
|
||||
};
|
||||
|
||||
|
|
@ -131,18 +134,7 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
|
|||
mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
|
||||
|
||||
rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
|
||||
rdiv = rdiv + 1;
|
||||
odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
|
||||
switch (odiv) {
|
||||
case 0:
|
||||
odiv = 2;
|
||||
break;
|
||||
case 1:
|
||||
odiv = 3;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Sometimes, the recalculated rate has deviation due to
|
||||
|
|
@ -160,6 +152,20 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
|
|||
if (rate)
|
||||
return (unsigned long)rate;
|
||||
|
||||
if (!rdiv)
|
||||
rdiv = rdiv + 1;
|
||||
|
||||
switch (odiv) {
|
||||
case 0:
|
||||
odiv = 2;
|
||||
break;
|
||||
case 1:
|
||||
odiv = 3;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Fvco = Fref * (MFI + MFN / MFD) */
|
||||
fvco = fvco * mfi * mfd + fvco * mfn;
|
||||
do_div(fvco, mfd * rdiv * odiv);
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@ static const struct imx93_clk_ccgr {
|
|||
{ IMX93_CLK_A55_GATE, "a55", "a55_root", 0x8000, },
|
||||
/* M33 critical clk for system run */
|
||||
{ IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL },
|
||||
{ IMX93_CLK_ADC1_GATE, "adc1", "osc_24m", 0x82c0, },
|
||||
{ IMX93_CLK_ADC1_GATE, "adc1", "adc_root", 0x82c0, },
|
||||
{ IMX93_CLK_WDOG1_GATE, "wdog1", "osc_24m", 0x8300, },
|
||||
{ IMX93_CLK_WDOG2_GATE, "wdog2", "osc_24m", 0x8340, },
|
||||
{ IMX93_CLK_WDOG3_GATE, "wdog3", "osc_24m", 0x8380, },
|
||||
|
|
@ -160,7 +160,7 @@ static const struct imx93_clk_ccgr {
|
|||
{ IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, },
|
||||
{ IMX93_CLK_MU_A_GATE, "mu_a", "bus_aon_root", 0x84c0, },
|
||||
{ IMX93_CLK_MU_B_GATE, "mu_b", "bus_aon_root", 0x8500, },
|
||||
{ IMX93_CLK_EDMA1_GATE, "edma1", "wakeup_axi_root", 0x8540, },
|
||||
{ IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, },
|
||||
{ IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, },
|
||||
{ IMX93_CLK_FLEXSPI1_GATE, "flexspi", "flexspi_root", 0x8640, },
|
||||
{ IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, },
|
||||
|
|
@ -219,7 +219,7 @@ static const struct imx93_clk_ccgr {
|
|||
{ IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, },
|
||||
{ IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, },
|
||||
{ IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, },
|
||||
{ IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_apb_root", 0x9700, },
|
||||
{ IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_axi_root", 0x9700, },
|
||||
{ IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, },
|
||||
{ IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, },
|
||||
{ IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "osc_24m", 0x9a80, },
|
||||
|
|
|
|||
|
|
@ -166,6 +166,7 @@ config IPQ_LCC_806X
|
|||
|
||||
config IPQ_GCC_8074
|
||||
tristate "IPQ8074 Global Clock Controller"
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for global clock controller on ipq8074 devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
|
|
@ -608,6 +609,13 @@ config SM_CAMCC_8250
|
|||
Support for the camera clock controller on SM8250 devices.
|
||||
Say Y if you want to support camera devices and camera functionality.
|
||||
|
||||
config SM_CAMCC_8450
|
||||
tristate "SM8450 Camera Clock Controller"
|
||||
select SM_GCC_8450
|
||||
help
|
||||
Support for the camera clock controller on SM8450 devices.
|
||||
Say Y if you want to support camera devices and camera functionality.
|
||||
|
||||
config SM_DISPCC_6125
|
||||
tristate "SM6125 Display Clock Controller"
|
||||
depends on SM_GCC_6125
|
||||
|
|
@ -618,11 +626,11 @@ config SM_DISPCC_6125
|
|||
splash screen
|
||||
|
||||
config SM_DISPCC_8250
|
||||
tristate "SM8150 and SM8250 Display Clock Controller"
|
||||
depends on SM_GCC_8150 || SM_GCC_8250
|
||||
tristate "SM8150/SM8250/SM8350 Display Clock Controller"
|
||||
depends on SM_GCC_8150 || SM_GCC_8250 || SM_GCC_8350
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
SM8150 and SM8250 devices.
|
||||
SM8150/SM8250/SM8350 devices.
|
||||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen.
|
||||
|
||||
|
|
@ -712,6 +720,14 @@ config SM_GPUCC_8250
|
|||
Say Y if you want to support graphics controller devices and
|
||||
functionality such as 3D graphics.
|
||||
|
||||
config SM_GPUCC_8350
|
||||
tristate "SM8350 Graphics Clock Controller"
|
||||
select SM_GCC_8350
|
||||
help
|
||||
Support for the graphics clock controller on SM8350 devices.
|
||||
Say Y if you want to support graphics controller devices and
|
||||
functionality such as 3D graphics.
|
||||
|
||||
config SM_VIDEOCC_8150
|
||||
tristate "SM8150 Video Clock Controller"
|
||||
select SM_GCC_8150
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
|
|||
clk-qcom-y += clk-regmap-divider.o
|
||||
clk-qcom-y += clk-regmap-mux.o
|
||||
clk-qcom-y += clk-regmap-mux-div.o
|
||||
clk-qcom-y += clk-regmap-phy-mux.o
|
||||
clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
|
||||
clk-qcom-y += clk-hfpll.o
|
||||
clk-qcom-y += reset.o
|
||||
|
|
@ -88,6 +89,7 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
|
|||
obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
|
||||
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
|
||||
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
|
||||
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
|
||||
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
|
||||
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
|
||||
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
|
||||
|
|
@ -101,6 +103,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
|
|||
obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
|
||||
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
|
||||
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
|
||||
obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
|
||||
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
|
||||
|
|
|
|||
|
|
@ -1534,6 +1534,8 @@ static struct clk_branch cam_cc_sys_tmr_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct gdsc titan_top_gdsc;
|
||||
|
||||
static struct gdsc bps_gdsc = {
|
||||
.gdscr = 0x6004,
|
||||
.pd = {
|
||||
|
|
@ -1567,6 +1569,7 @@ static struct gdsc ife_0_gdsc = {
|
|||
.name = "ife_0_gdsc",
|
||||
},
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.parent = &titan_top_gdsc.pd,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
|
|
@ -1576,6 +1579,7 @@ static struct gdsc ife_1_gdsc = {
|
|||
.name = "ife_1_gdsc",
|
||||
},
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.parent = &titan_top_gdsc.pd,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2205,6 +2205,8 @@ static struct clk_branch cam_cc_sleep_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct gdsc titan_top_gdsc;
|
||||
|
||||
static struct gdsc bps_gdsc = {
|
||||
.gdscr = 0x7004,
|
||||
.pd = {
|
||||
|
|
@ -2238,6 +2240,7 @@ static struct gdsc ife_0_gdsc = {
|
|||
.name = "ife_0_gdsc",
|
||||
},
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.parent = &titan_top_gdsc.pd,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
|
|
@ -2247,6 +2250,7 @@ static struct gdsc ife_1_gdsc = {
|
|||
.name = "ife_1_gdsc",
|
||||
},
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.parent = &titan_top_gdsc.pd,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
|
|
@ -2440,17 +2444,7 @@ static struct platform_driver cam_cc_sm8250_driver = {
|
|||
},
|
||||
};
|
||||
|
||||
static int __init cam_cc_sm8250_init(void)
|
||||
{
|
||||
return platform_driver_register(&cam_cc_sm8250_driver);
|
||||
}
|
||||
subsys_initcall(cam_cc_sm8250_init);
|
||||
|
||||
static void __exit cam_cc_sm8250_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&cam_cc_sm8250_driver);
|
||||
}
|
||||
module_exit(cam_cc_sm8250_exit);
|
||||
module_platform_driver(cam_cc_sm8250_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QTI CAMCC SM8250 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
2856
drivers/clk/qcom/camcc-sm8450.c
Normal file
2856
drivers/clk/qcom/camcc-sm8450.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
|
|||
[PLL_OFF_TEST_CTL_U] = 0x30,
|
||||
[PLL_OFF_TEST_CTL_U1] = 0x34,
|
||||
},
|
||||
[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
|
||||
[PLL_OFF_OPMODE] = 0x04,
|
||||
[PLL_OFF_STATUS] = 0x0c,
|
||||
[PLL_OFF_L_VAL] = 0x10,
|
||||
[PLL_OFF_USER_CTL] = 0x14,
|
||||
[PLL_OFF_USER_CTL_U] = 0x18,
|
||||
[PLL_OFF_CONFIG_CTL] = 0x1c,
|
||||
[PLL_OFF_CONFIG_CTL_U] = 0x20,
|
||||
[PLL_OFF_CONFIG_CTL_U1] = 0x24,
|
||||
[PLL_OFF_TEST_CTL] = 0x28,
|
||||
[PLL_OFF_TEST_CTL_U] = 0x2c,
|
||||
},
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
|
||||
|
||||
|
|
@ -191,8 +203,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
|
|||
#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
|
||||
|
||||
/* LUCID EVO PLL specific settings and offsets */
|
||||
#define LUCID_EVO_PCAL_NOT_DONE BIT(8)
|
||||
#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
|
||||
#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
|
||||
#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
|
||||
|
||||
/* ZONDA PLL specific */
|
||||
#define ZONDA_PLL_OUT_MASK 0xf
|
||||
|
|
@ -1439,7 +1453,7 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
|
|||
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
|
||||
|
||||
/**
|
||||
* clk_lucid_pll_configure - configure the lucid pll
|
||||
* clk_trion_pll_configure - configure the trion pll
|
||||
*
|
||||
* @pll: clk alpha pll
|
||||
* @regmap: register map
|
||||
|
|
@ -1823,7 +1837,7 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
|
|||
.round_rate = clk_alpha_pll_round_rate,
|
||||
.set_rate = alpha_pll_lucid_5lpe_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops);
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
|
||||
|
||||
const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
|
||||
.enable = alpha_pll_lucid_5lpe_enable,
|
||||
|
|
@ -1832,14 +1846,14 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
|
|||
.recalc_rate = clk_trion_pll_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_round_rate,
|
||||
};
|
||||
EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_5lpe_ops);
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
|
||||
|
||||
const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
|
||||
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
|
||||
.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
|
||||
|
||||
void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config)
|
||||
|
|
@ -1992,7 +2006,33 @@ const struct clk_ops clk_alpha_pll_zonda_ops = {
|
|||
.round_rate = clk_alpha_pll_round_rate,
|
||||
.set_rate = clk_zonda_pll_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
|
||||
|
||||
void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config)
|
||||
{
|
||||
u32 lval = config->l;
|
||||
|
||||
lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
|
||||
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
|
||||
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
|
||||
|
||||
/* Disable PLL output */
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
|
||||
|
||||
/* Set operation mode to STANDBY and de-assert the reset */
|
||||
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
|
||||
|
||||
static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
|
||||
{
|
||||
|
|
@ -2079,6 +2119,31 @@ static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
|
|||
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
|
||||
}
|
||||
|
||||
static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
struct clk_hw *p;
|
||||
u32 val = 0;
|
||||
int ret;
|
||||
|
||||
/* Return early if calibration is not needed. */
|
||||
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
|
||||
if (!(val & LUCID_EVO_PCAL_NOT_DONE))
|
||||
return 0;
|
||||
|
||||
p = clk_hw_get_parent(hw);
|
||||
if (!p)
|
||||
return -EINVAL;
|
||||
|
||||
ret = alpha_pll_lucid_evo_enable(hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
alpha_pll_lucid_evo_disable(hw);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
|
|
@ -2114,3 +2179,72 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
|
|||
.set_rate = clk_lucid_evo_pll_postdiv_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
|
||||
|
||||
const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
|
||||
.prepare = alpha_pll_lucid_evo_prepare,
|
||||
.enable = alpha_pll_lucid_evo_enable,
|
||||
.disable = alpha_pll_lucid_evo_disable,
|
||||
.is_enabled = clk_trion_pll_is_enabled,
|
||||
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_round_rate,
|
||||
.set_rate = alpha_pll_lucid_5lpe_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
|
||||
|
||||
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config)
|
||||
{
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
|
||||
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
|
||||
|
||||
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
|
||||
|
||||
regmap_update_bits(regmap, PLL_MODE(pll),
|
||||
PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
|
||||
PLL_RESET_N | PLL_BYPASSNL);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
|
||||
|
||||
static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
u32 l;
|
||||
|
||||
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
|
||||
|
||||
return parent_rate * l;
|
||||
}
|
||||
|
||||
static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
unsigned long min_freq, max_freq;
|
||||
u32 l;
|
||||
u64 a;
|
||||
|
||||
rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
|
||||
if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
|
||||
return rate;
|
||||
|
||||
min_freq = pll->vco_table[0].min_freq;
|
||||
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
|
||||
|
||||
return clamp(rate, min_freq, max_freq);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
|
||||
.enable = alpha_pll_lucid_5lpe_enable,
|
||||
.disable = alpha_pll_lucid_5lpe_disable,
|
||||
.is_enabled = clk_trion_pll_is_enabled,
|
||||
.recalc_rate = clk_rivian_evo_pll_recalc_rate,
|
||||
.round_rate = clk_rivian_evo_pll_round_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ enum {
|
|||
CLK_ALPHA_PLL_TYPE_AGERA,
|
||||
CLK_ALPHA_PLL_TYPE_ZONDA,
|
||||
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
|
||||
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
|
||||
CLK_ALPHA_PLL_TYPE_MAX,
|
||||
};
|
||||
|
||||
|
|
@ -152,9 +153,14 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
|
|||
|
||||
extern const struct clk_ops clk_alpha_pll_zonda_ops;
|
||||
#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
|
||||
|
||||
extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
|
||||
|
||||
extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
|
||||
#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
|
||||
|
||||
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
|
|
@ -168,6 +174,9 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
|||
|
||||
void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
|
||||
void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -72,13 +72,16 @@ static void __clk_hfpll_enable(struct clk_hw *hw)
|
|||
regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
|
||||
|
||||
/* Wait for PLL to lock. */
|
||||
if (hd->status_reg) {
|
||||
do {
|
||||
regmap_read(regmap, hd->status_reg, &val);
|
||||
} while (!(val & BIT(hd->lock_bit)));
|
||||
} else {
|
||||
if (hd->status_reg)
|
||||
/*
|
||||
* Busy wait. Should never timeout, we add a timeout to
|
||||
* prevent any sort of stall.
|
||||
*/
|
||||
regmap_read_poll_timeout(regmap, hd->status_reg, val,
|
||||
!(val & BIT(hd->lock_bit)), 0,
|
||||
100 * USEC_PER_MSEC);
|
||||
else
|
||||
udelay(60);
|
||||
}
|
||||
|
||||
/* Enable PLL output. */
|
||||
regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
|
||||
|
|
|
|||
|
|
@ -18,13 +18,23 @@
|
|||
static DEFINE_SPINLOCK(krait_clock_reg_lock);
|
||||
|
||||
#define LPL_SHIFT 8
|
||||
#define SECCLKAGD BIT(4)
|
||||
|
||||
static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 regval;
|
||||
|
||||
spin_lock_irqsave(&krait_clock_reg_lock, flags);
|
||||
|
||||
regval = krait_get_l2_indirect_reg(mux->offset);
|
||||
|
||||
/* apq/ipq8064 Errata: disable sec_src clock gating during switch. */
|
||||
if (mux->disable_sec_src_gating) {
|
||||
regval |= SECCLKAGD;
|
||||
krait_set_l2_indirect_reg(mux->offset, regval);
|
||||
}
|
||||
|
||||
regval &= ~(mux->mask << mux->shift);
|
||||
regval |= (sel & mux->mask) << mux->shift;
|
||||
if (mux->lpl) {
|
||||
|
|
@ -32,11 +42,22 @@ static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
|
|||
regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
|
||||
}
|
||||
krait_set_l2_indirect_reg(mux->offset, regval);
|
||||
spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
|
||||
|
||||
/* apq/ipq8064 Errata: re-enabled sec_src clock gating. */
|
||||
if (mux->disable_sec_src_gating) {
|
||||
regval &= ~SECCLKAGD;
|
||||
krait_set_l2_indirect_reg(mux->offset, regval);
|
||||
}
|
||||
|
||||
/* Wait for switch to complete. */
|
||||
mb();
|
||||
udelay(1);
|
||||
|
||||
/*
|
||||
* Unlock now to make sure the mux register is not
|
||||
* modified while switching to the new parent.
|
||||
*/
|
||||
spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
|
||||
}
|
||||
|
||||
static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ struct krait_mux_clk {
|
|||
u8 safe_sel;
|
||||
u8 old_index;
|
||||
bool reparent;
|
||||
bool disable_sec_src_gating;
|
||||
|
||||
struct clk_hw hw;
|
||||
struct notifier_block clk_nb;
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/rational.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/math64.h>
|
||||
#include <linux/minmax.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <asm/div64.h>
|
||||
|
|
@ -437,7 +438,7 @@ static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
|
|||
static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
u32 notn_m, n, m, d, not2d, mask, duty_per;
|
||||
u32 notn_m, n, m, d, not2d, mask, duty_per, cfg;
|
||||
int ret;
|
||||
|
||||
/* Duty-cycle cannot be modified for non-MND RCGs */
|
||||
|
|
@ -448,6 +449,11 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
|
|||
|
||||
regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m);
|
||||
regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
|
||||
regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
|
||||
|
||||
/* Duty-cycle cannot be modified if MND divider is in bypass mode. */
|
||||
if (!(cfg & CFG_MODE_MASK))
|
||||
return -EINVAL;
|
||||
|
||||
n = (~(notn_m) + m) & mask;
|
||||
|
||||
|
|
@ -456,9 +462,11 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
|
|||
/* Calculate 2d value */
|
||||
d = DIV_ROUND_CLOSEST(n * duty_per * 2, 100);
|
||||
|
||||
/* Check bit widths of 2d. If D is too big reduce duty cycle. */
|
||||
if (d > mask)
|
||||
d = mask;
|
||||
/*
|
||||
* Check bit widths of 2d. If D is too big reduce duty cycle.
|
||||
* Also make sure it is never zero.
|
||||
*/
|
||||
d = clamp_val(d, 1, mask);
|
||||
|
||||
if ((d / 2) > (n - m))
|
||||
d = (n - m) * 2;
|
||||
|
|
|
|||
62
drivers/clk/qcom/clk-regmap-phy-mux.c
Normal file
62
drivers/clk/qcom/clk-regmap-phy-mux.c
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2022, Linaro Ltd.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-phy-mux.h"
|
||||
|
||||
#define PHY_MUX_MASK GENMASK(1, 0)
|
||||
#define PHY_MUX_PHY_SRC 0
|
||||
#define PHY_MUX_REF_SRC 2
|
||||
|
||||
static inline struct clk_regmap_phy_mux *to_clk_regmap_phy_mux(struct clk_regmap *clkr)
|
||||
{
|
||||
return container_of(clkr, struct clk_regmap_phy_mux, clkr);
|
||||
}
|
||||
|
||||
static int phy_mux_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_regmap *clkr = to_clk_regmap(hw);
|
||||
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
|
||||
unsigned int val;
|
||||
|
||||
regmap_read(clkr->regmap, phy_mux->reg, &val);
|
||||
val = FIELD_GET(PHY_MUX_MASK, val);
|
||||
|
||||
WARN_ON(val != PHY_MUX_PHY_SRC && val != PHY_MUX_REF_SRC);
|
||||
|
||||
return val == PHY_MUX_PHY_SRC;
|
||||
}
|
||||
|
||||
static int phy_mux_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_regmap *clkr = to_clk_regmap(hw);
|
||||
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
|
||||
|
||||
return regmap_update_bits(clkr->regmap, phy_mux->reg,
|
||||
PHY_MUX_MASK,
|
||||
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC));
|
||||
}
|
||||
|
||||
static void phy_mux_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_regmap *clkr = to_clk_regmap(hw);
|
||||
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
|
||||
|
||||
regmap_update_bits(clkr->regmap, phy_mux->reg,
|
||||
PHY_MUX_MASK,
|
||||
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC));
|
||||
}
|
||||
|
||||
const struct clk_ops clk_regmap_phy_mux_ops = {
|
||||
.enable = phy_mux_enable,
|
||||
.disable = phy_mux_disable,
|
||||
.is_enabled = phy_mux_is_enabled,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_regmap_phy_mux_ops);
|
||||
33
drivers/clk/qcom/clk-regmap-phy-mux.h
Normal file
33
drivers/clk/qcom/clk-regmap-phy-mux.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2022, Linaro Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __QCOM_CLK_REGMAP_PHY_MUX_H__
|
||||
#define __QCOM_CLK_REGMAP_PHY_MUX_H__
|
||||
|
||||
#include "clk-regmap.h"
|
||||
|
||||
/*
|
||||
* A clock implementation for PHY pipe and symbols clock muxes.
|
||||
*
|
||||
* If the clock is running off the from-PHY source, report it as enabled.
|
||||
* Report it as disabled otherwise (if it uses reference source).
|
||||
*
|
||||
* This way the PHY will disable the pipe clock before turning off the GDSC,
|
||||
* which in turn would lead to disabling corresponding pipe_clk_src (and thus
|
||||
* it being parked to a safe, reference clock source). And vice versa, after
|
||||
* enabling the GDSC the PHY will enable the pipe clock, which would cause
|
||||
* pipe_clk_src to be switched from a safe source to the working one.
|
||||
*
|
||||
* For some platforms this should be used for the UFS symbol_clk_src clocks
|
||||
* too.
|
||||
*/
|
||||
struct clk_regmap_phy_mux {
|
||||
u32 reg;
|
||||
struct clk_regmap clkr;
|
||||
};
|
||||
|
||||
extern const struct clk_ops clk_regmap_phy_mux_ops;
|
||||
|
||||
#endif
|
||||
|
|
@ -23,6 +23,14 @@
|
|||
#define QCOM_RPM_SCALING_ENABLE_ID 0x2
|
||||
#define QCOM_RPM_XO_MODE_ON 0x2
|
||||
|
||||
static const struct clk_parent_data gcc_pxo[] = {
|
||||
{ .fw_name = "pxo", .name = "pxo_board" },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_cxo[] = {
|
||||
{ .fw_name = "cxo", .name = "cxo_board" },
|
||||
};
|
||||
|
||||
#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
|
||||
static struct clk_rpm _platform##_##_active; \
|
||||
static struct clk_rpm _platform##_##_name = { \
|
||||
|
|
@ -32,8 +40,8 @@
|
|||
.hw.init = &(struct clk_init_data){ \
|
||||
.ops = &clk_rpm_ops, \
|
||||
.name = #_name, \
|
||||
.parent_names = (const char *[]){ "pxo_board" }, \
|
||||
.num_parents = 1, \
|
||||
.parent_data = gcc_pxo, \
|
||||
.num_parents = ARRAY_SIZE(gcc_pxo), \
|
||||
}, \
|
||||
}; \
|
||||
static struct clk_rpm _platform##_##_active = { \
|
||||
|
|
@ -44,8 +52,8 @@
|
|||
.hw.init = &(struct clk_init_data){ \
|
||||
.ops = &clk_rpm_ops, \
|
||||
.name = #_active, \
|
||||
.parent_names = (const char *[]){ "pxo_board" }, \
|
||||
.num_parents = 1, \
|
||||
.parent_data = gcc_pxo, \
|
||||
.num_parents = ARRAY_SIZE(gcc_pxo), \
|
||||
}, \
|
||||
}
|
||||
|
||||
|
|
@ -56,8 +64,8 @@
|
|||
.hw.init = &(struct clk_init_data){ \
|
||||
.ops = &clk_rpm_xo_ops, \
|
||||
.name = #_name, \
|
||||
.parent_names = (const char *[]){ "cxo_board" }, \
|
||||
.num_parents = 1, \
|
||||
.parent_data = gcc_cxo, \
|
||||
.num_parents = ARRAY_SIZE(gcc_cxo), \
|
||||
}, \
|
||||
}
|
||||
|
||||
|
|
@ -68,8 +76,8 @@
|
|||
.hw.init = &(struct clk_init_data){ \
|
||||
.ops = &clk_rpm_fixed_ops, \
|
||||
.name = #_name, \
|
||||
.parent_names = (const char *[]){ "pxo" }, \
|
||||
.num_parents = 1, \
|
||||
.parent_data = gcc_pxo, \
|
||||
.num_parents = ARRAY_SIZE(gcc_pxo), \
|
||||
}, \
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -274,6 +274,11 @@ static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
|
|||
cmd.addr = c->res_addr;
|
||||
cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
|
||||
|
||||
/*
|
||||
* Send only an active only state request. RPMh continues to
|
||||
* use the active state when we're in sleep/wake state as long
|
||||
* as the sleep/wake state has never been set.
|
||||
*/
|
||||
ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable);
|
||||
if (ret) {
|
||||
dev_err(c->dev, "set active state of %s failed: (%d)\n",
|
||||
|
|
|
|||
|
|
@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = {
|
|||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
static struct pll_vco lucid_5lpe_vco[] = {
|
||||
{ 249600000, 1750000000, 0 },
|
||||
};
|
||||
|
||||
static struct alpha_pll_config disp_cc_pll0_config = {
|
||||
.l = 0x47,
|
||||
.alpha = 0xE000,
|
||||
|
|
@ -1134,7 +1138,6 @@ static struct gdsc mdss_gdsc = {
|
|||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = HW_CTRL,
|
||||
.supply = "mmcx",
|
||||
};
|
||||
|
||||
static struct clk_regmap *disp_cc_sm8250_clocks[] = {
|
||||
|
|
@ -1228,6 +1231,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = {
|
|||
{ .compatible = "qcom,sc8180x-dispcc" },
|
||||
{ .compatible = "qcom,sm8150-dispcc" },
|
||||
{ .compatible = "qcom,sm8250-dispcc" },
|
||||
{ .compatible = "qcom,sm8350-dispcc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
|
||||
|
|
@ -1258,7 +1262,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
/* note: trion == lucid, except for the prepare() op */
|
||||
/* Apply differences for SM8150 and SM8350 */
|
||||
BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
|
||||
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
|
||||
of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
|
||||
|
|
@ -1270,6 +1274,62 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
|
|||
disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
|
||||
disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
|
||||
disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
|
||||
} else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
|
||||
static struct clk_rcg2 * const rcgs[] = {
|
||||
&disp_cc_mdss_byte0_clk_src,
|
||||
&disp_cc_mdss_byte1_clk_src,
|
||||
&disp_cc_mdss_dp_aux1_clk_src,
|
||||
&disp_cc_mdss_dp_aux_clk_src,
|
||||
&disp_cc_mdss_dp_link1_clk_src,
|
||||
&disp_cc_mdss_dp_link_clk_src,
|
||||
&disp_cc_mdss_dp_pixel1_clk_src,
|
||||
&disp_cc_mdss_dp_pixel2_clk_src,
|
||||
&disp_cc_mdss_dp_pixel_clk_src,
|
||||
&disp_cc_mdss_esc0_clk_src,
|
||||
&disp_cc_mdss_mdp_clk_src,
|
||||
&disp_cc_mdss_pclk0_clk_src,
|
||||
&disp_cc_mdss_pclk1_clk_src,
|
||||
&disp_cc_mdss_rot_clk_src,
|
||||
&disp_cc_mdss_vsync_clk_src,
|
||||
};
|
||||
static struct clk_regmap_div * const divs[] = {
|
||||
&disp_cc_mdss_byte0_div_clk_src,
|
||||
&disp_cc_mdss_byte1_div_clk_src,
|
||||
&disp_cc_mdss_dp_link1_div_clk_src,
|
||||
&disp_cc_mdss_dp_link_div_clk_src,
|
||||
};
|
||||
unsigned int i;
|
||||
static bool offset_applied;
|
||||
|
||||
/*
|
||||
* note: trion == lucid, except for the prepare() op
|
||||
* only apply the offsets once (in case of deferred probe)
|
||||
*/
|
||||
if (!offset_applied) {
|
||||
for (i = 0; i < ARRAY_SIZE(rcgs); i++)
|
||||
rcgs[i]->cmd_rcgr -= 4;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(divs); i++) {
|
||||
divs[i]->reg -= 4;
|
||||
divs[i]->width = 4;
|
||||
}
|
||||
|
||||
disp_cc_mdss_ahb_clk.halt_reg -= 4;
|
||||
disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
|
||||
|
||||
offset_applied = true;
|
||||
}
|
||||
|
||||
disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
|
||||
|
||||
disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c;
|
||||
disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
|
||||
disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
|
||||
disp_cc_pll0.vco_table = lucid_5lpe_vco;
|
||||
disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c;
|
||||
disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
|
||||
disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
|
||||
disp_cc_pll1.vco_table = lucid_5lpe_vco;
|
||||
}
|
||||
|
||||
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include "clk-alpha-pll.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "clk-regmap-mux.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
|
|
@ -662,6 +663,7 @@ static struct clk_branch gcc_sleep_clk_src = {
|
|||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
|
@ -1788,8 +1790,10 @@ static struct clk_regmap_div nss_port4_tx_div_clk_src = {
|
|||
static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
|
||||
F(25000000, P_UNIPHY0_RX, 5, 0, 0),
|
||||
F(78125000, P_UNIPHY1_RX, 4, 0, 0),
|
||||
F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
|
||||
F(125000000, P_UNIPHY0_RX, 1, 0, 0),
|
||||
F(156250000, P_UNIPHY1_RX, 2, 0, 0),
|
||||
F(312500000, P_UNIPHY1_RX, 1, 0, 0),
|
||||
{ }
|
||||
|
|
@ -1828,8 +1832,10 @@ static struct clk_regmap_div nss_port5_rx_div_clk_src = {
|
|||
static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
|
||||
F(25000000, P_UNIPHY0_TX, 5, 0, 0),
|
||||
F(78125000, P_UNIPHY1_TX, 4, 0, 0),
|
||||
F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
|
||||
F(125000000, P_UNIPHY0_TX, 1, 0, 0),
|
||||
F(156250000, P_UNIPHY1_TX, 2, 0, 0),
|
||||
F(312500000, P_UNIPHY1_TX, 1, 0, 0),
|
||||
{ }
|
||||
|
|
@ -1867,8 +1873,10 @@ static struct clk_regmap_div nss_port5_tx_div_clk_src = {
|
|||
|
||||
static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(25000000, P_UNIPHY2_RX, 5, 0, 0),
|
||||
F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
|
||||
F(78125000, P_UNIPHY2_RX, 4, 0, 0),
|
||||
F(125000000, P_UNIPHY2_RX, 1, 0, 0),
|
||||
F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
|
||||
F(156250000, P_UNIPHY2_RX, 2, 0, 0),
|
||||
F(312500000, P_UNIPHY2_RX, 1, 0, 0),
|
||||
|
|
@ -1907,8 +1915,10 @@ static struct clk_regmap_div nss_port6_rx_div_clk_src = {
|
|||
|
||||
static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(25000000, P_UNIPHY2_TX, 5, 0, 0),
|
||||
F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
|
||||
F(78125000, P_UNIPHY2_TX, 4, 0, 0),
|
||||
F(125000000, P_UNIPHY2_TX, 1, 0, 0),
|
||||
F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
|
||||
F(156250000, P_UNIPHY2_TX, 2, 0, 0),
|
||||
F(312500000, P_UNIPHY2_TX, 1, 0, 0),
|
||||
|
|
@ -3174,6 +3184,24 @@ static struct clk_branch gcc_nss_ptp_ref_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_crypto_ppe_clk = {
|
||||
.halt_reg = 0x68310,
|
||||
.halt_bit = 31,
|
||||
.clkr = {
|
||||
.enable_reg = 0x68310,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_crypto_ppe_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"nss_ppe_clk_src"
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_nssnoc_ce_apb_clk = {
|
||||
.halt_reg = 0x6830c,
|
||||
.clkr = {
|
||||
|
|
@ -3346,6 +3374,7 @@ static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
|
|||
|
||||
static struct clk_branch gcc_ubi0_ahb_clk = {
|
||||
.halt_reg = 0x6820c,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x6820c,
|
||||
.enable_mask = BIT(0),
|
||||
|
|
@ -3363,6 +3392,7 @@ static struct clk_branch gcc_ubi0_ahb_clk = {
|
|||
|
||||
static struct clk_branch gcc_ubi0_axi_clk = {
|
||||
.halt_reg = 0x68200,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x68200,
|
||||
.enable_mask = BIT(0),
|
||||
|
|
@ -3380,6 +3410,7 @@ static struct clk_branch gcc_ubi0_axi_clk = {
|
|||
|
||||
static struct clk_branch gcc_ubi0_nc_axi_clk = {
|
||||
.halt_reg = 0x68204,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x68204,
|
||||
.enable_mask = BIT(0),
|
||||
|
|
@ -3397,6 +3428,7 @@ static struct clk_branch gcc_ubi0_nc_axi_clk = {
|
|||
|
||||
static struct clk_branch gcc_ubi0_core_clk = {
|
||||
.halt_reg = 0x68210,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x68210,
|
||||
.enable_mask = BIT(0),
|
||||
|
|
@ -3414,6 +3446,7 @@ static struct clk_branch gcc_ubi0_core_clk = {
|
|||
|
||||
static struct clk_branch gcc_ubi0_mpt_clk = {
|
||||
.halt_reg = 0x68208,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x68208,
|
||||
.enable_mask = BIT(0),
|
||||
|
|
@ -3431,6 +3464,7 @@ static struct clk_branch gcc_ubi0_mpt_clk = {
|
|||
|
||||
static struct clk_branch gcc_ubi1_ahb_clk = {
|
||||
.halt_reg = 0x6822c,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x6822c,
|
||||
.enable_mask = BIT(0),
|
||||
|
|
@ -3448,6 +3482,7 @@ static struct clk_branch gcc_ubi1_ahb_clk = {
|
|||
|
||||
static struct clk_branch gcc_ubi1_axi_clk = {
|
||||
.halt_reg = 0x68220,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x68220,
|
||||
.enable_mask = BIT(0),
|
||||
|
|
@ -3465,6 +3500,7 @@ static struct clk_branch gcc_ubi1_axi_clk = {
|
|||
|
||||
static struct clk_branch gcc_ubi1_nc_axi_clk = {
|
||||
.halt_reg = 0x68224,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x68224,
|
||||
.enable_mask = BIT(0),
|
||||
|
|
@ -3482,6 +3518,7 @@ static struct clk_branch gcc_ubi1_nc_axi_clk = {
|
|||
|
||||
static struct clk_branch gcc_ubi1_core_clk = {
|
||||
.halt_reg = 0x68230,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x68230,
|
||||
.enable_mask = BIT(0),
|
||||
|
|
@ -3499,6 +3536,7 @@ static struct clk_branch gcc_ubi1_core_clk = {
|
|||
|
||||
static struct clk_branch gcc_ubi1_mpt_clk = {
|
||||
.halt_reg = 0x68228,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x68228,
|
||||
.enable_mask = BIT(0),
|
||||
|
|
@ -4371,6 +4409,49 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct gdsc usb0_gdsc = {
|
||||
.gdscr = 0x3e078,
|
||||
.pd = {
|
||||
.name = "usb0_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct gdsc usb1_gdsc = {
|
||||
.gdscr = 0x3f078,
|
||||
.pd = {
|
||||
.name = "usb1_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config ubi32_pll_config = {
|
||||
.l = 0x4e,
|
||||
.config_ctl_val = 0x200d4aa8,
|
||||
.config_ctl_hi_val = 0x3c2,
|
||||
.main_output_mask = BIT(0),
|
||||
.aux_output_mask = BIT(1),
|
||||
.pre_div_val = 0x0,
|
||||
.pre_div_mask = BIT(12),
|
||||
.post_div_val = 0x0,
|
||||
.post_div_mask = GENMASK(9, 8),
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config nss_crypto_pll_config = {
|
||||
.l = 0x3e,
|
||||
.alpha = 0x0,
|
||||
.alpha_hi = 0x80,
|
||||
.config_ctl_val = 0x4001055b,
|
||||
.main_output_mask = BIT(0),
|
||||
.pre_div_val = 0x0,
|
||||
.pre_div_mask = GENMASK(14, 12),
|
||||
.post_div_val = 0x1 << 8,
|
||||
.post_div_mask = GENMASK(11, 8),
|
||||
.vco_mask = GENMASK(21, 20),
|
||||
.vco_val = 0x0,
|
||||
.alpha_en_mask = BIT(24),
|
||||
};
|
||||
|
||||
static struct clk_hw *gcc_ipq8074_hws[] = {
|
||||
&gpll0_out_main_div2.hw,
|
||||
&gpll6_out_main_div2.hw,
|
||||
|
|
@ -4609,6 +4690,7 @@ static struct clk_regmap *gcc_ipq8074_clks[] = {
|
|||
[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
|
||||
[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
|
||||
[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
|
||||
[GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map gcc_ipq8074_resets[] = {
|
||||
|
|
@ -4746,6 +4828,11 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = {
|
|||
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
|
||||
};
|
||||
|
||||
static struct gdsc *gcc_ipq8074_gdscs[] = {
|
||||
[USB0_GDSC] = &usb0_gdsc,
|
||||
[USB1_GDSC] = &usb1_gdsc,
|
||||
};
|
||||
|
||||
static const struct of_device_id gcc_ipq8074_match_table[] = {
|
||||
{ .compatible = "qcom,gcc-ipq8074" },
|
||||
{ }
|
||||
|
|
@ -4768,11 +4855,26 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = {
|
|||
.num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
|
||||
.clk_hws = gcc_ipq8074_hws,
|
||||
.num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
|
||||
.gdscs = gcc_ipq8074_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
|
||||
};
|
||||
|
||||
static int gcc_ipq8074_probe(struct platform_device *pdev)
|
||||
{
|
||||
return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
/* SW Workaround for UBI32 Huayra PLL */
|
||||
regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
|
||||
|
||||
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
|
||||
clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
|
||||
&nss_crypto_pll_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver gcc_ipq8074_driver = {
|
||||
|
|
|
|||
|
|
@ -765,7 +765,20 @@ static struct clk_rcg2 cci_clk_src = {
|
|||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* This is a frequency table for "General Purpose" clocks.
|
||||
* These clocks can be muxed to the SoC pins and may be used by
|
||||
* external devices. They're often used as PWM source.
|
||||
*
|
||||
* See comment at ftbl_gcc_gp1_3_clk.
|
||||
*/
|
||||
static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
|
||||
F(10000, P_XO, 16, 1, 120),
|
||||
F(100000, P_XO, 16, 1, 12),
|
||||
F(500000, P_GPLL0, 16, 1, 100),
|
||||
F(1000000, P_GPLL0, 16, 1, 50),
|
||||
F(2500000, P_GPLL0, 16, 1, 20),
|
||||
F(5000000, P_GPLL0, 16, 1, 10),
|
||||
F(100000000, P_GPLL0, 8, 0, 0),
|
||||
F(200000000, P_GPLL0, 4, 0, 0),
|
||||
{ }
|
||||
|
|
@ -927,7 +940,29 @@ static struct clk_rcg2 crypto_clk_src = {
|
|||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* This is a frequency table for "General Purpose" clocks.
|
||||
* These clocks can be muxed to the SoC pins and may be used by
|
||||
* external devices. They're often used as PWM source.
|
||||
*
|
||||
* Please note that MND divider must be enabled for duty-cycle
|
||||
* control to be possible. (M != N) Also since D register is configured
|
||||
* with a value multiplied by 2, and duty cycle is calculated as
|
||||
* (2 * D) % 2^W
|
||||
* DutyCycle = ----------------
|
||||
* 2 * (N % 2^W)
|
||||
* (where W = .mnd_width)
|
||||
* N must be half or less than maximum value for the register.
|
||||
* Otherwise duty-cycle control would be limited.
|
||||
* (e.g. for 8-bit NMD N should be less than 128)
|
||||
*/
|
||||
static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
|
||||
F(10000, P_XO, 16, 1, 120),
|
||||
F(100000, P_XO, 16, 1, 12),
|
||||
F(500000, P_GPLL0, 16, 1, 100),
|
||||
F(1000000, P_GPLL0, 16, 1, 50),
|
||||
F(2500000, P_GPLL0, 16, 1, 20),
|
||||
F(5000000, P_GPLL0, 16, 1, 10),
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -632,7 +632,7 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = {
|
|||
};
|
||||
|
||||
static struct clk_rcg2 bimc_ddr_clk_src = {
|
||||
.cmd_rcgr = 0x32004,
|
||||
.cmd_rcgr = 0x32024,
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_xo_gpll0_bimc_map,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
|
|
@ -644,6 +644,18 @@ static struct clk_rcg2 bimc_ddr_clk_src = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
|
||||
.cmd_rcgr = 0x2600c,
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_xo_gpll0_gpll6a_map,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "system_mm_noc_bfdcd_clk_src",
|
||||
.parent_data = gcc_xo_gpll0_gpll6a_parent_data,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
|
||||
F(40000000, P_GPLL0, 10, 1, 2),
|
||||
F(80000000, P_GPLL0, 10, 0, 0),
|
||||
|
|
@ -1002,7 +1014,8 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
|
|||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(37500000, P_GPLL0, 1, 3, 64),
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
@ -1142,6 +1155,9 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
|
|||
|
||||
static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
|
||||
F(160000000, P_GPLL0, 5, 0, 0),
|
||||
F(200000000, P_GPLL0, 4, 0, 0),
|
||||
F(228570000, P_GPLL0, 3.5, 0, 0),
|
||||
F(266670000, P_GPLL0, 3, 0, 0),
|
||||
F(320000000, P_GPLL0, 2.5, 0, 0),
|
||||
F(465000000, P_GPLL2, 2, 0, 0),
|
||||
{ }
|
||||
|
|
@ -1290,6 +1306,8 @@ static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
|
|||
F(50000000, P_GPLL0_AUX, 16, 0, 0),
|
||||
F(80000000, P_GPLL0_AUX, 10, 0, 0),
|
||||
F(100000000, P_GPLL0_AUX, 8, 0, 0),
|
||||
F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
|
||||
F(153600000, P_GPLL0, 4, 0, 0),
|
||||
F(160000000, P_GPLL0_AUX, 5, 0, 0),
|
||||
F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
|
||||
F(200000000, P_GPLL0_AUX, 4, 0, 0),
|
||||
|
|
@ -1462,7 +1480,9 @@ static struct clk_rcg2 bimc_gpu_clk_src = {
|
|||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
|
||||
F(57140000, P_GPLL0, 14, 0, 0),
|
||||
F(80000000, P_GPLL0, 10, 0, 0),
|
||||
F(100000000, P_GPLL0, 8, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
@ -1823,9 +1843,9 @@ static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
|
|||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
|
||||
F(100000000, P_GPLL0, 8, 0, 0),
|
||||
F(160000000, P_GPLL0, 5, 0, 0),
|
||||
F(228570000, P_GPLL0, 3.5, 0, 0),
|
||||
F(133330000, P_GPLL0, 6, 0, 0),
|
||||
F(200000000, P_GPLL0, 4, 0, 0),
|
||||
F(266670000, P_GPLL0, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
@ -2441,7 +2461,7 @@ static struct clk_branch gcc_camss_jpeg_axi_clk = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_camss_jpeg_axi_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
|
||||
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2645,7 +2665,7 @@ static struct clk_branch gcc_camss_vfe_axi_clk = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_camss_vfe_axi_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
|
||||
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2801,7 +2821,7 @@ static struct clk_branch gcc_mdss_axi_clk = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_mdss_axi_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
|
||||
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -3193,7 +3213,7 @@ static struct clk_branch gcc_mdp_tbu_clk = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_mdp_tbu_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
|
||||
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -3211,7 +3231,7 @@ static struct clk_branch gcc_venus_tbu_clk = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_venus_tbu_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
|
||||
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -3229,7 +3249,7 @@ static struct clk_branch gcc_vfe_tbu_clk = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_vfe_tbu_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
|
||||
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -3247,7 +3267,7 @@ static struct clk_branch gcc_jpeg_tbu_clk = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_jpeg_tbu_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
|
||||
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -3484,7 +3504,7 @@ static struct clk_branch gcc_venus0_axi_clk = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_venus0_axi_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
|
||||
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -3623,6 +3643,7 @@ static struct clk_regmap *gcc_msm8939_clocks[] = {
|
|||
[GPLL2_VOTE] = &gpll2_vote,
|
||||
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
|
||||
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
|
||||
[SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr,
|
||||
[CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
|
||||
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
|
||||
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
|
||||
|
|
|
|||
|
|
@ -3641,6 +3641,9 @@ static int gcc_msm8960_probe(struct platform_device *pdev)
|
|||
hfpll_l2.d = &hfpll_l2_8064_data;
|
||||
}
|
||||
|
||||
if (of_get_available_child_count(pdev->dev.of_node) != 0)
|
||||
return devm_of_platform_populate(&pdev->dev);
|
||||
|
||||
tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
|
||||
NULL, 0);
|
||||
if (IS_ERR(tsens))
|
||||
|
|
@ -3655,7 +3658,8 @@ static int gcc_msm8960_remove(struct platform_device *pdev)
|
|||
{
|
||||
struct platform_device *tsens = platform_get_drvdata(pdev);
|
||||
|
||||
platform_device_unregister(tsens);
|
||||
if (tsens)
|
||||
platform_device_unregister(tsens);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -52,7 +52,9 @@ static struct clk_alpha_pll_postdiv gpll0 = {
|
|||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpll0",
|
||||
.parent_names = (const char *[]) { "gpll0_early" },
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpll0_early.clkr.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_postdiv_ops,
|
||||
},
|
||||
|
|
@ -81,7 +83,9 @@ static struct clk_alpha_pll_postdiv gpll4 = {
|
|||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpll4",
|
||||
.parent_names = (const char *[]) { "gpll4_early" },
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpll4_early.clkr.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_postdiv_ops,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include "clk-rcg.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "clk-regmap-mux.h"
|
||||
#include "clk-regmap-phy-mux.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
|
@ -255,26 +256,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = {
|
|||
{ .hw = &gcc_gpll0_out_even.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_6[] = {
|
||||
{ P_PCIE_0_PIPE_CLK, 0 },
|
||||
{ P_BI_TCXO, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_parent_data_6[] = {
|
||||
{ .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_7[] = {
|
||||
{ P_PCIE_1_PIPE_CLK, 0 },
|
||||
{ P_BI_TCXO, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_parent_data_7[] = {
|
||||
{ .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" },
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_8[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GCC_GPLL0_OUT_MAIN, 1 },
|
||||
|
|
@ -369,32 +350,32 @@ static const struct clk_parent_data gcc_parent_data_15[] = {
|
|||
{ .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw },
|
||||
};
|
||||
|
||||
static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
|
||||
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
|
||||
.reg = 0x6b054,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.parent_map = gcc_parent_map_6,
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_pcie_0_pipe_clk_src",
|
||||
.parent_data = gcc_parent_data_6,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
|
||||
.ops = &clk_regmap_mux_closest_ops,
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "pcie_0_pipe_clk",
|
||||
.name = "pcie_0_pipe_clk",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_regmap_phy_mux_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
|
||||
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
|
||||
.reg = 0x8d054,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.parent_map = gcc_parent_map_7,
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_pcie_1_pipe_clk_src",
|
||||
.parent_data = gcc_parent_data_7,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
|
||||
.ops = &clk_regmap_mux_closest_ops,
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "pcie_1_pipe_clk",
|
||||
.name = "pcie_1_pipe_clk",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_regmap_phy_mux_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "clk-regmap-mux.h"
|
||||
#include "clk-regmap-phy-mux.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
|
@ -82,11 +83,6 @@ enum {
|
|||
P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC,
|
||||
P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC,
|
||||
P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC,
|
||||
P_PCIE_2A_PIPE_CLK,
|
||||
P_PCIE_2B_PIPE_CLK,
|
||||
P_PCIE_3A_PIPE_CLK,
|
||||
P_PCIE_3B_PIPE_CLK,
|
||||
P_PCIE_4_PIPE_CLK,
|
||||
P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
|
||||
P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
|
||||
P_QUSB4PHY_GCC_USB4_RX0_CLK,
|
||||
|
|
@ -351,56 +347,6 @@ static const struct clk_parent_data gcc_parent_data_9[] = {
|
|||
{ .hw = &gcc_gpll0_out_even.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_10[] = {
|
||||
{ P_PCIE_2A_PIPE_CLK, 0 },
|
||||
{ P_BI_TCXO, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_parent_data_10[] = {
|
||||
{ .index = DT_PCIE_2A_PIPE_CLK },
|
||||
{ .index = DT_BI_TCXO },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_11[] = {
|
||||
{ P_PCIE_2B_PIPE_CLK, 0 },
|
||||
{ P_BI_TCXO, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_parent_data_11[] = {
|
||||
{ .index = DT_PCIE_2B_PIPE_CLK },
|
||||
{ .index = DT_BI_TCXO },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_12[] = {
|
||||
{ P_PCIE_3A_PIPE_CLK, 0 },
|
||||
{ P_BI_TCXO, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_parent_data_12[] = {
|
||||
{ .index = DT_PCIE_3A_PIPE_CLK },
|
||||
{ .index = DT_BI_TCXO },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_13[] = {
|
||||
{ P_PCIE_3B_PIPE_CLK, 0 },
|
||||
{ P_BI_TCXO, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_parent_data_13[] = {
|
||||
{ .index = DT_PCIE_3B_PIPE_CLK },
|
||||
{ .index = DT_BI_TCXO },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_14[] = {
|
||||
{ P_PCIE_4_PIPE_CLK, 0 },
|
||||
{ P_BI_TCXO, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_parent_data_14[] = {
|
||||
{ .index = DT_PCIE_4_PIPE_CLK },
|
||||
{ .index = DT_BI_TCXO },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_15[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GCC_GPLL0_OUT_MAIN, 1 },
|
||||
|
|
@ -741,77 +687,72 @@ static const struct clk_parent_data gcc_parent_data_41[] = {
|
|||
{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },
|
||||
};
|
||||
|
||||
static struct clk_regmap_mux gcc_pcie_2a_pipe_clk_src = {
|
||||
static struct clk_regmap_phy_mux gcc_pcie_2a_pipe_clk_src = {
|
||||
.reg = 0x9d05c,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.parent_map = gcc_parent_map_10,
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gcc_pcie_2a_pipe_clk_src",
|
||||
.parent_data = gcc_parent_data_10,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
|
||||
.ops = &clk_regmap_mux_closest_ops,
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_PCIE_2A_PIPE_CLK,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_regmap_phy_mux_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_mux gcc_pcie_2b_pipe_clk_src = {
|
||||
static struct clk_regmap_phy_mux gcc_pcie_2b_pipe_clk_src = {
|
||||
.reg = 0x9e05c,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.parent_map = gcc_parent_map_11,
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gcc_pcie_2b_pipe_clk_src",
|
||||
.parent_data = gcc_parent_data_11,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
|
||||
.ops = &clk_regmap_mux_closest_ops,
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_PCIE_2B_PIPE_CLK,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_regmap_phy_mux_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_mux gcc_pcie_3a_pipe_clk_src = {
|
||||
static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = {
|
||||
.reg = 0xa005c,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.parent_map = gcc_parent_map_12,
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gcc_pcie_3a_pipe_clk_src",
|
||||
.parent_data = gcc_parent_data_12,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
|
||||
.ops = &clk_regmap_mux_closest_ops,
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_PCIE_3A_PIPE_CLK,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_regmap_phy_mux_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_mux gcc_pcie_3b_pipe_clk_src = {
|
||||
static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = {
|
||||
.reg = 0xa205c,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.parent_map = gcc_parent_map_13,
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gcc_pcie_3b_pipe_clk_src",
|
||||
.parent_data = gcc_parent_data_13,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
|
||||
.ops = &clk_regmap_mux_closest_ops,
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_PCIE_3B_PIPE_CLK,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_regmap_phy_mux_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_mux gcc_pcie_4_pipe_clk_src = {
|
||||
static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
|
||||
.reg = 0x6b05c,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.parent_map = gcc_parent_map_14,
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gcc_pcie_4_pipe_clk_src",
|
||||
.parent_data = gcc_parent_data_14,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_14),
|
||||
.ops = &clk_regmap_mux_closest_ops,
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_PCIE_4_PIPE_CLK,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_regmap_phy_mux_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
|
@ -6807,58 +6748,79 @@ static struct clk_branch gcc_video_vcodec_throttle_clk = {
|
|||
|
||||
static struct gdsc pcie_0_tunnel_gdsc = {
|
||||
.gdscr = 0xa4004,
|
||||
.collapse_ctrl = 0x52128,
|
||||
.collapse_mask = BIT(0),
|
||||
.pd = {
|
||||
.name = "pcie_0_tunnel_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_1_tunnel_gdsc = {
|
||||
.gdscr = 0x8d004,
|
||||
.collapse_ctrl = 0x52128,
|
||||
.collapse_mask = BIT(1),
|
||||
.pd = {
|
||||
.name = "pcie_1_tunnel_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_2a_gdsc = {
|
||||
.gdscr = 0x9d004,
|
||||
.collapse_ctrl = 0x52128,
|
||||
.collapse_mask = BIT(2),
|
||||
.pd = {
|
||||
.name = "pcie_2a_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_2b_gdsc = {
|
||||
.gdscr = 0x9e004,
|
||||
.collapse_ctrl = 0x52128,
|
||||
.collapse_mask = BIT(3),
|
||||
.pd = {
|
||||
.name = "pcie_2b_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_3a_gdsc = {
|
||||
.gdscr = 0xa0004,
|
||||
.collapse_ctrl = 0x52128,
|
||||
.collapse_mask = BIT(4),
|
||||
.pd = {
|
||||
.name = "pcie_3a_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_3b_gdsc = {
|
||||
.gdscr = 0xa2004,
|
||||
.collapse_ctrl = 0x52128,
|
||||
.collapse_mask = BIT(5),
|
||||
.pd = {
|
||||
.name = "pcie_3b_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_4_gdsc = {
|
||||
.gdscr = 0x6b004,
|
||||
.collapse_ctrl = 0x52128,
|
||||
.collapse_mask = BIT(6),
|
||||
.pd = {
|
||||
.name = "pcie_4_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc ufs_card_gdsc = {
|
||||
|
|
|
|||
|
|
@ -2558,7 +2558,7 @@ static int gcc_sm6350_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
return qcom_cc_really_probe(pdev, &gcc_sm6350_desc, regmap);;
|
||||
return qcom_cc_really_probe(pdev, &gcc_sm6350_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver gcc_sm6350_driver = {
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "clk-regmap-mux.h"
|
||||
#include "clk-regmap-phy-mux.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
||||
|
|
@ -26,9 +27,7 @@ enum {
|
|||
P_GCC_GPLL0_OUT_MAIN,
|
||||
P_GCC_GPLL4_OUT_MAIN,
|
||||
P_GCC_GPLL9_OUT_MAIN,
|
||||
P_PCIE_0_PIPE_CLK,
|
||||
P_PCIE_1_PHY_AUX_CLK,
|
||||
P_PCIE_1_PIPE_CLK,
|
||||
P_SLEEP_CLK,
|
||||
P_UFS_PHY_RX_SYMBOL_0_CLK,
|
||||
P_UFS_PHY_RX_SYMBOL_1_CLK,
|
||||
|
|
@ -153,16 +152,6 @@ static const struct clk_parent_data gcc_parent_data_3[] = {
|
|||
{ .fw_name = "bi_tcxo" },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_4[] = {
|
||||
{ P_PCIE_0_PIPE_CLK, 0 },
|
||||
{ P_BI_TCXO, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_parent_data_4[] = {
|
||||
{ .fw_name = "pcie_0_pipe_clk", },
|
||||
{ .fw_name = "bi_tcxo", },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_5[] = {
|
||||
{ P_PCIE_1_PHY_AUX_CLK, 0 },
|
||||
{ P_BI_TCXO, 2 },
|
||||
|
|
@ -173,16 +162,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = {
|
|||
{ .fw_name = "bi_tcxo" },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_6[] = {
|
||||
{ P_PCIE_1_PIPE_CLK, 0 },
|
||||
{ P_BI_TCXO, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_parent_data_6[] = {
|
||||
{ .fw_name = "pcie_1_pipe_clk" },
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_7[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GCC_GPLL0_OUT_MAIN, 1 },
|
||||
|
|
@ -239,17 +218,16 @@ static const struct clk_parent_data gcc_parent_data_11[] = {
|
|||
{ .fw_name = "bi_tcxo" },
|
||||
};
|
||||
|
||||
static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
|
||||
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
|
||||
.reg = 0x7b060,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.parent_map = gcc_parent_map_4,
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_pcie_0_pipe_clk_src",
|
||||
.parent_data = gcc_parent_data_4,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
|
||||
.ops = &clk_regmap_mux_closest_ops,
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "pcie_0_pipe_clk",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_regmap_phy_mux_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
|
@ -269,17 +247,16 @@ static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
|
||||
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
|
||||
.reg = 0x9d064,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.parent_map = gcc_parent_map_6,
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_pcie_1_pipe_clk_src",
|
||||
.parent_data = gcc_parent_data_6,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
|
||||
.ops = &clk_regmap_mux_closest_ops,
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "pcie_1_pipe_clk",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_regmap_phy_mux_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -132,10 +132,29 @@ static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
|
|||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
|
||||
{
|
||||
u32 reg, mask;
|
||||
int ret;
|
||||
|
||||
if (sc->collapse_mask) {
|
||||
reg = sc->collapse_ctrl;
|
||||
mask = sc->collapse_mask;
|
||||
} else {
|
||||
reg = sc->gdscr;
|
||||
mask = SW_COLLAPSE_MASK;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
|
||||
{
|
||||
int ret;
|
||||
u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
|
||||
|
||||
if (status == GDSC_ON && sc->rsupply) {
|
||||
ret = regulator_enable(sc->rsupply);
|
||||
|
|
@ -143,9 +162,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF);
|
||||
|
||||
/* If disabling votable gdscs, don't poll on status */
|
||||
if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
|
||||
|
|
@ -420,13 +437,20 @@ static int gdsc_init(struct gdsc *sc)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* ...and the power-domain */
|
||||
ret = gdsc_pm_runtime_get(sc);
|
||||
if (ret) {
|
||||
if (sc->rsupply)
|
||||
regulator_disable(sc->rsupply);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Votable GDSCs can be ON due to Vote from other masters.
|
||||
* If a Votable GDSC is ON, make sure we have a Vote.
|
||||
*/
|
||||
if (sc->flags & VOTABLE) {
|
||||
ret = regmap_update_bits(sc->regmap, sc->gdscr,
|
||||
SW_COLLAPSE_MASK, val);
|
||||
ret = gdsc_update_collapse_bit(sc, false);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@ struct reset_controller_dev;
|
|||
* @pd: generic power domain
|
||||
* @regmap: regmap for MMIO accesses
|
||||
* @gdscr: gsdc control register
|
||||
* @collapse_ctrl: APCS collapse-vote register
|
||||
* @collapse_mask: APCS collapse-vote mask
|
||||
* @gds_hw_ctrl: gds_hw_ctrl register
|
||||
* @cxcs: offsets of branch registers to toggle mem/periph bits in
|
||||
* @cxc_count: number of @cxcs
|
||||
|
|
@ -35,6 +37,8 @@ struct gdsc {
|
|||
struct generic_pm_domain *parent;
|
||||
struct regmap *regmap;
|
||||
unsigned int gdscr;
|
||||
unsigned int collapse_ctrl;
|
||||
unsigned int collapse_mask;
|
||||
unsigned int gds_hw_ctrl;
|
||||
unsigned int clamp_io_ctrl;
|
||||
unsigned int *cxcs;
|
||||
|
|
|
|||
637
drivers/clk/qcom/gpucc-sm8350.c
Normal file
637
drivers/clk/qcom/gpucc-sm8350.c
Normal file
|
|
@ -0,0 +1,637 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022, Linaro Limited
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-pll.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "common.h"
|
||||
#include "clk-regmap-mux.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
P_GPLL0_OUT_MAIN_DIV,
|
||||
P_GPU_CC_PLL0_OUT_MAIN,
|
||||
P_GPU_CC_PLL1_OUT_MAIN,
|
||||
};
|
||||
|
||||
static struct pll_vco lucid_5lpe_vco[] = {
|
||||
{ 249600000, 1750000000, 0 },
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config gpu_cc_pll0_config = {
|
||||
.l = 0x18,
|
||||
.alpha = 0x6000,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00002261,
|
||||
.config_ctl_hi1_val = 0x2a9a699c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000000,
|
||||
.test_ctl_hi1_val = 0x01800000,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
.user_ctl_hi1_val = 0x00000000,
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent = {
|
||||
.fw_name = "bi_tcxo",
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = lucid_5lpe_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "gpu_cc_pll0",
|
||||
.parent_data = &gpu_cc_parent,
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_5lpe_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config gpu_cc_pll1_config = {
|
||||
.l = 0x1a,
|
||||
.alpha = 0xaaa,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00002261,
|
||||
.config_ctl_hi1_val = 0x2a9a699c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000000,
|
||||
.test_ctl_hi1_val = 0x01800000,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
.user_ctl_hi1_val = 0x00000000,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll1 = {
|
||||
.offset = 0x100,
|
||||
.vco_table = lucid_5lpe_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_pll1",
|
||||
.parent_data = &gpu_cc_parent,
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_5lpe_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
|
||||
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
|
||||
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
|
||||
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
|
||||
.cmd_rcgr = 0x1120,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gmu_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
|
||||
F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
|
||||
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
|
||||
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_hub_clk_src = {
|
||||
.cmd_rcgr = 0x117c,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
|
||||
.reg = 0x11c0,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_ahb_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
|
||||
.reg = 0x11bc,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_cx_int_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_ahb_clk = {
|
||||
.halt_reg = 0x1078,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1078,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cb_clk = {
|
||||
.halt_reg = 0x1170,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1170,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cb_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_crc_ahb_clk = {
|
||||
.halt_reg = 0x107c,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x107c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_crc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_apb_clk = {
|
||||
.halt_reg = 0x1088,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1088,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_apb_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gmu_clk = {
|
||||
.halt_reg = 0x1098,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1098,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_qdss_at_clk = {
|
||||
.halt_reg = 0x1080,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1080,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_qdss_at_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_qdss_trig_clk = {
|
||||
.halt_reg = 0x1094,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1094,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_qdss_trig_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = {
|
||||
.halt_reg = 0x1084,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1084,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_qdss_tsctr_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
|
||||
.halt_reg = 0x108c,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x108c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_snoc_dvm_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_aon_clk = {
|
||||
.halt_reg = 0x1004,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_aon_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_clk = {
|
||||
.halt_reg = 0x109c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x109c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_freq_measure_clk = {
|
||||
.halt_reg = 0x120c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x120c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_freq_measure_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gmu_clk = {
|
||||
.halt_reg = 0x1064,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1064,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = {
|
||||
.halt_reg = 0x105c,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x105c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_qdss_tsctr_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_vsense_clk = {
|
||||
.halt_reg = 0x1058,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1058,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_vsense_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
|
||||
.halt_reg = 0x5000,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x5000,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_aon_clk = {
|
||||
.halt_reg = 0x1178,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1178,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_aon_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_cx_int_clk = {
|
||||
.halt_reg = 0x1204,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1204,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_cx_int_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
|
||||
.halt_reg = 0x802c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x802c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
|
||||
.halt_reg = 0x8030,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8030,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_sleep_clk = {
|
||||
.halt_reg = 0x1090,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1090,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_sleep_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc gpu_cx_gdsc = {
|
||||
.gdscr = 0x106c,
|
||||
.gds_hw_ctrl = 0x1540,
|
||||
.pd = {
|
||||
.name = "gpu_cx_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc gpu_gx_gdsc = {
|
||||
.gdscr = 0x100c,
|
||||
.clamp_io_ctrl = 0x1508,
|
||||
.pd = {
|
||||
.name = "gpu_gx_gdsc",
|
||||
.power_on = gdsc_gx_do_nothing_enable,
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gpu_cc_sm8350_clocks[] = {
|
||||
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
|
||||
[GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
|
||||
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
|
||||
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
|
||||
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
|
||||
[GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr,
|
||||
[GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr,
|
||||
[GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr,
|
||||
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
|
||||
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
|
||||
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
|
||||
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
|
||||
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
|
||||
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
|
||||
[GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr,
|
||||
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
|
||||
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
|
||||
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
|
||||
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
|
||||
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
|
||||
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
|
||||
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
|
||||
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
|
||||
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
|
||||
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
|
||||
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
|
||||
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map gpu_cc_sm8350_resets[] = {
|
||||
[GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
|
||||
[GPUCC_GPU_CC_CB_BCR] = { 0x116c },
|
||||
[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
|
||||
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 },
|
||||
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
|
||||
[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
|
||||
[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
|
||||
[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
|
||||
};
|
||||
|
||||
static struct gdsc *gpu_cc_sm8350_gdscs[] = {
|
||||
[GPU_CX_GDSC] = &gpu_cx_gdsc,
|
||||
[GPU_GX_GDSC] = &gpu_gx_gdsc,
|
||||
};
|
||||
|
||||
static const struct regmap_config gpu_cc_sm8350_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x8030,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc gpu_cc_sm8350_desc = {
|
||||
.config = &gpu_cc_sm8350_regmap_config,
|
||||
.clks = gpu_cc_sm8350_clocks,
|
||||
.num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks),
|
||||
.resets = gpu_cc_sm8350_resets,
|
||||
.num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets),
|
||||
.gdscs = gpu_cc_sm8350_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs),
|
||||
};
|
||||
|
||||
static int gpu_cc_sm8350_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc);
|
||||
if (IS_ERR(regmap)) {
|
||||
dev_err(&pdev->dev, "Failed to map gpu cc registers\n");
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
||||
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap);
|
||||
}
|
||||
|
||||
static const struct of_device_id gpu_cc_sm8350_match_table[] = {
|
||||
{ .compatible = "qcom,sm8350-gpucc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table);
|
||||
|
||||
static struct platform_driver gpu_cc_sm8350_driver = {
|
||||
.probe = gpu_cc_sm8350_probe,
|
||||
.driver = {
|
||||
.name = "sm8350-gpucc",
|
||||
.of_match_table = gpu_cc_sm8350_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init gpu_cc_sm8350_init(void)
|
||||
{
|
||||
return platform_driver_register(&gpu_cc_sm8350_driver);
|
||||
}
|
||||
subsys_initcall(gpu_cc_sm8350_init);
|
||||
|
||||
static void __exit gpu_cc_sm8350_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&gpu_cc_sm8350_driver);
|
||||
}
|
||||
module_exit(gpu_cc_sm8350_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -139,6 +139,14 @@ krait_add_sec_mux(struct device *dev, int id, const char *s,
|
|||
mux->hw.init = &init;
|
||||
mux->safe_sel = 0;
|
||||
|
||||
/* Checking for qcom,krait-cc-v1 or qcom,krait-cc-v2 is not
|
||||
* enough to limit this to apq/ipq8064. Directly check machine
|
||||
* compatible to correctly handle this errata.
|
||||
*/
|
||||
if (of_machine_is_compatible("qcom,ipq8064") ||
|
||||
of_machine_is_compatible("qcom,apq8064"))
|
||||
mux->disable_sec_src_gating = true;
|
||||
|
||||
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
|
||||
if (!init.name)
|
||||
return -ENOMEM;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -277,7 +277,6 @@ static struct gdsc mvs0c_gdsc = {
|
|||
},
|
||||
.flags = 0,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.supply = "mmcx",
|
||||
};
|
||||
|
||||
static struct gdsc mvs1c_gdsc = {
|
||||
|
|
@ -287,7 +286,6 @@ static struct gdsc mvs1c_gdsc = {
|
|||
},
|
||||
.flags = 0,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.supply = "mmcx",
|
||||
};
|
||||
|
||||
static struct gdsc mvs0_gdsc = {
|
||||
|
|
@ -297,7 +295,6 @@ static struct gdsc mvs0_gdsc = {
|
|||
},
|
||||
.flags = HW_CTRL,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.supply = "mmcx",
|
||||
};
|
||||
|
||||
static struct gdsc mvs1_gdsc = {
|
||||
|
|
@ -307,7 +304,6 @@ static struct gdsc mvs1_gdsc = {
|
|||
},
|
||||
.flags = HW_CTRL,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.supply = "mmcx",
|
||||
};
|
||||
|
||||
static struct clk_regmap *video_cc_sm8250_clocks[] = {
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
struct r8a73a4_cpg {
|
||||
struct clk_onecell_data data;
|
||||
spinlock_t lock;
|
||||
void __iomem *reg;
|
||||
};
|
||||
|
||||
#define CPG_CKSCR 0xc0
|
||||
|
|
@ -59,7 +58,7 @@ static const struct clk_div_table div4_div_table[] = {
|
|||
|
||||
static struct clk * __init
|
||||
r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
|
||||
const char *name)
|
||||
void __iomem *base, const char *name)
|
||||
{
|
||||
const struct clk_div_table *table = NULL;
|
||||
const char *parent_name;
|
||||
|
|
@ -69,7 +68,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
|
|||
|
||||
|
||||
if (!strcmp(name, "main")) {
|
||||
u32 ckscr = readl(cpg->reg + CPG_CKSCR);
|
||||
u32 ckscr = readl(base + CPG_CKSCR);
|
||||
|
||||
switch ((ckscr >> 28) & 3) {
|
||||
case 0: /* extal1 */
|
||||
|
|
@ -93,14 +92,14 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
|
|||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
u32 value = readl(cpg->reg + CPG_PLL0CR);
|
||||
u32 value = readl(base + CPG_PLL0CR);
|
||||
|
||||
parent_name = "main";
|
||||
mult = ((value >> 24) & 0x7f) + 1;
|
||||
if (value & BIT(20))
|
||||
div = 2;
|
||||
} else if (!strcmp(name, "pll1")) {
|
||||
u32 value = readl(cpg->reg + CPG_PLL1CR);
|
||||
u32 value = readl(base + CPG_PLL1CR);
|
||||
|
||||
parent_name = "main";
|
||||
/* XXX: enable bit? */
|
||||
|
|
@ -123,7 +122,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
|
|||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
value = readl(cpg->reg + cr);
|
||||
value = readl(base + cr);
|
||||
switch ((value >> 5) & 7) {
|
||||
case 0:
|
||||
parent_name = "main";
|
||||
|
|
@ -159,7 +158,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
|
|||
shift = 0;
|
||||
}
|
||||
div *= 32;
|
||||
mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
|
||||
mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);
|
||||
} else {
|
||||
struct div4_clk *c;
|
||||
|
||||
|
|
@ -181,7 +180,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
|
|||
mult, div);
|
||||
} else {
|
||||
return clk_register_divider_table(NULL, name, parent_name, 0,
|
||||
cpg->reg + reg, shift, 4, 0,
|
||||
base + reg, shift, 4, 0,
|
||||
table, &cpg->lock);
|
||||
}
|
||||
}
|
||||
|
|
@ -189,6 +188,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
|
|||
static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct r8a73a4_cpg *cpg;
|
||||
void __iomem *base;
|
||||
struct clk **clks;
|
||||
unsigned int i;
|
||||
int num_clks;
|
||||
|
|
@ -213,8 +213,8 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
|
|||
cpg->data.clks = clks;
|
||||
cpg->data.clk_num = num_clks;
|
||||
|
||||
cpg->reg = of_iomap(np, 0);
|
||||
if (WARN_ON(cpg->reg == NULL))
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(base == NULL))
|
||||
return;
|
||||
|
||||
for (i = 0; i < num_clks; ++i) {
|
||||
|
|
@ -224,7 +224,7 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
|
|||
of_property_read_string_index(np, "clock-output-names", i,
|
||||
&name);
|
||||
|
||||
clk = r8a73a4_cpg_register_clock(np, cpg, name);
|
||||
clk = r8a73a4_cpg_register_clock(np, cpg, base, name);
|
||||
if (IS_ERR(clk))
|
||||
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
|
||||
__func__, np, name, PTR_ERR(clk));
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
struct r8a7740_cpg {
|
||||
struct clk_onecell_data data;
|
||||
spinlock_t lock;
|
||||
void __iomem *reg;
|
||||
};
|
||||
|
||||
#define CPG_FRQCRA 0x00
|
||||
|
|
@ -61,7 +60,7 @@ static u32 cpg_mode __initdata;
|
|||
|
||||
static struct clk * __init
|
||||
r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
|
||||
const char *name)
|
||||
void __iomem *base, const char *name)
|
||||
{
|
||||
const struct clk_div_table *table = NULL;
|
||||
const char *parent_name;
|
||||
|
|
@ -96,20 +95,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
|
|||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
u32 value = readl(cpg->reg + CPG_FRQCRC);
|
||||
u32 value = readl(base + CPG_FRQCRC);
|
||||
parent_name = "system";
|
||||
mult = ((value >> 24) & 0x7f) + 1;
|
||||
} else if (!strcmp(name, "pllc1")) {
|
||||
u32 value = readl(cpg->reg + CPG_FRQCRA);
|
||||
u32 value = readl(base + CPG_FRQCRA);
|
||||
parent_name = "system";
|
||||
mult = ((value >> 24) & 0x7f) + 1;
|
||||
div = 2;
|
||||
} else if (!strcmp(name, "pllc2")) {
|
||||
u32 value = readl(cpg->reg + CPG_PLLC2CR);
|
||||
u32 value = readl(base + CPG_PLLC2CR);
|
||||
parent_name = "system";
|
||||
mult = ((value >> 24) & 0x3f) + 1;
|
||||
} else if (!strcmp(name, "usb24s")) {
|
||||
u32 value = readl(cpg->reg + CPG_USBCKCR);
|
||||
u32 value = readl(base + CPG_USBCKCR);
|
||||
if (value & BIT(7))
|
||||
/* extal2 */
|
||||
parent_name = of_clk_get_parent_name(np, 1);
|
||||
|
|
@ -137,7 +136,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
|
|||
mult, div);
|
||||
} else {
|
||||
return clk_register_divider_table(NULL, name, parent_name, 0,
|
||||
cpg->reg + reg, shift, 4, 0,
|
||||
base + reg, shift, 4, 0,
|
||||
table, &cpg->lock);
|
||||
}
|
||||
}
|
||||
|
|
@ -145,6 +144,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
|
|||
static void __init r8a7740_cpg_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct r8a7740_cpg *cpg;
|
||||
void __iomem *base;
|
||||
struct clk **clks;
|
||||
unsigned int i;
|
||||
int num_clks;
|
||||
|
|
@ -172,8 +172,8 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np)
|
|||
cpg->data.clks = clks;
|
||||
cpg->data.clk_num = num_clks;
|
||||
|
||||
cpg->reg = of_iomap(np, 0);
|
||||
if (WARN_ON(cpg->reg == NULL))
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(base == NULL))
|
||||
return;
|
||||
|
||||
for (i = 0; i < num_clks; ++i) {
|
||||
|
|
@ -183,7 +183,7 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np)
|
|||
of_property_read_string_index(np, "clock-output-names", i,
|
||||
&name);
|
||||
|
||||
clk = r8a7740_cpg_register_clock(np, cpg, name);
|
||||
clk = r8a7740_cpg_register_clock(np, cpg, base, name);
|
||||
if (IS_ERR(clk))
|
||||
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
|
||||
__func__, np, name, PTR_ERR(clk));
|
||||
|
|
|
|||
|
|
@ -11,12 +11,6 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
struct r8a7778_cpg {
|
||||
struct clk_onecell_data data;
|
||||
spinlock_t lock;
|
||||
void __iomem *reg;
|
||||
};
|
||||
|
||||
/* PLL multipliers per bits 11, 12, and 18 of MODEMR */
|
||||
static const struct {
|
||||
unsigned long plla_mult;
|
||||
|
|
@ -47,8 +41,7 @@ static u32 cpg_mode_rates __initdata;
|
|||
static u32 cpg_mode_divs __initdata;
|
||||
|
||||
static struct clk * __init
|
||||
r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
|
||||
const char *name)
|
||||
r8a7778_cpg_register_clock(struct device_node *np, const char *name)
|
||||
{
|
||||
if (!strcmp(name, "plla")) {
|
||||
return clk_register_fixed_factor(NULL, "plla",
|
||||
|
|
@ -77,7 +70,7 @@ r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
|
|||
|
||||
static void __init r8a7778_cpg_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct r8a7778_cpg *cpg;
|
||||
struct clk_onecell_data *data;
|
||||
struct clk **clks;
|
||||
unsigned int i;
|
||||
int num_clks;
|
||||
|
|
@ -100,23 +93,17 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
|
|||
return;
|
||||
}
|
||||
|
||||
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
|
||||
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
||||
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
|
||||
if (cpg == NULL || clks == NULL) {
|
||||
if (data == NULL || clks == NULL) {
|
||||
/* We're leaking memory on purpose, there's no point in cleaning
|
||||
* up as the system won't boot anyway.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
spin_lock_init(&cpg->lock);
|
||||
|
||||
cpg->data.clks = clks;
|
||||
cpg->data.clk_num = num_clks;
|
||||
|
||||
cpg->reg = of_iomap(np, 0);
|
||||
if (WARN_ON(cpg->reg == NULL))
|
||||
return;
|
||||
data->clks = clks;
|
||||
data->clk_num = num_clks;
|
||||
|
||||
for (i = 0; i < num_clks; ++i) {
|
||||
const char *name;
|
||||
|
|
@ -125,15 +112,15 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
|
|||
of_property_read_string_index(np, "clock-output-names", i,
|
||||
&name);
|
||||
|
||||
clk = r8a7778_cpg_register_clock(np, cpg, name);
|
||||
clk = r8a7778_cpg_register_clock(np, name);
|
||||
if (IS_ERR(clk))
|
||||
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
|
||||
__func__, np, name, PTR_ERR(clk));
|
||||
else
|
||||
cpg->data.clks[i] = clk;
|
||||
data->clks[i] = clk;
|
||||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, data);
|
||||
|
||||
cpg_mstp_add_clk_domain(np);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,12 +21,6 @@
|
|||
|
||||
#define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1)
|
||||
|
||||
struct r8a7779_cpg {
|
||||
struct clk_onecell_data data;
|
||||
spinlock_t lock;
|
||||
void __iomem *reg;
|
||||
};
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
|
@ -87,7 +81,7 @@ static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
|
|||
*/
|
||||
|
||||
static struct clk * __init
|
||||
r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
|
||||
r8a7779_cpg_register_clock(struct device_node *np,
|
||||
const struct cpg_clk_config *config,
|
||||
unsigned int plla_mult, const char *name)
|
||||
{
|
||||
|
|
@ -119,7 +113,7 @@ r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
|
|||
static void __init r8a7779_cpg_clocks_init(struct device_node *np)
|
||||
{
|
||||
const struct cpg_clk_config *config;
|
||||
struct r8a7779_cpg *cpg;
|
||||
struct clk_onecell_data *data;
|
||||
struct clk **clks;
|
||||
unsigned int i, plla_mult;
|
||||
int num_clks;
|
||||
|
|
@ -134,19 +128,17 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
|
|||
return;
|
||||
}
|
||||
|
||||
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
|
||||
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
||||
clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL);
|
||||
if (cpg == NULL || clks == NULL) {
|
||||
if (data == NULL || clks == NULL) {
|
||||
/* We're leaking memory on purpose, there's no point in cleaning
|
||||
* up as the system won't boot anyway.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
spin_lock_init(&cpg->lock);
|
||||
|
||||
cpg->data.clks = clks;
|
||||
cpg->data.clk_num = num_clks;
|
||||
data->clks = clks;
|
||||
data->clk_num = num_clks;
|
||||
|
||||
config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)];
|
||||
plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];
|
||||
|
|
@ -158,16 +150,15 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
|
|||
of_property_read_string_index(np, "clock-output-names", i,
|
||||
&name);
|
||||
|
||||
clk = r8a7779_cpg_register_clock(np, cpg, config,
|
||||
plla_mult, name);
|
||||
clk = r8a7779_cpg_register_clock(np, config, plla_mult, name);
|
||||
if (IS_ERR(clk))
|
||||
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
|
||||
__func__, np, name, PTR_ERR(clk));
|
||||
else
|
||||
cpg->data.clks[i] = clk;
|
||||
data->clks[i] = clk;
|
||||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, data);
|
||||
|
||||
cpg_mstp_add_clk_domain(np);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,11 +15,6 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
struct rz_cpg {
|
||||
struct clk_onecell_data data;
|
||||
void __iomem *reg;
|
||||
};
|
||||
|
||||
#define CPG_FRQCR 0x10
|
||||
#define CPG_FRQCR2 0x14
|
||||
|
||||
|
|
@ -49,7 +44,8 @@ static u16 __init rz_cpg_read_mode_pins(void)
|
|||
}
|
||||
|
||||
static struct clk * __init
|
||||
rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
|
||||
rz_cpg_register_clock(struct device_node *np, void __iomem *base,
|
||||
const char *name)
|
||||
{
|
||||
u32 val;
|
||||
unsigned mult;
|
||||
|
|
@ -65,7 +61,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na
|
|||
}
|
||||
|
||||
/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
|
||||
if (!cpg->reg)
|
||||
if (!base)
|
||||
return ERR_PTR(-ENXIO);
|
||||
|
||||
/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
|
||||
|
|
@ -73,9 +69,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na
|
|||
* let them run at fixed current speed and implement the details later.
|
||||
*/
|
||||
if (strcmp(name, "i") == 0)
|
||||
val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
|
||||
val = (readl(base + CPG_FRQCR) >> 8) & 3;
|
||||
else if (strcmp(name, "g") == 0)
|
||||
val = readl(cpg->reg + CPG_FRQCR2) & 3;
|
||||
val = readl(base + CPG_FRQCR2) & 3;
|
||||
else
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
|
|
@ -85,8 +81,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na
|
|||
|
||||
static void __init rz_cpg_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct rz_cpg *cpg;
|
||||
struct clk_onecell_data *data;
|
||||
struct clk **clks;
|
||||
void __iomem *base;
|
||||
unsigned i;
|
||||
int num_clks;
|
||||
|
||||
|
|
@ -94,14 +91,14 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
|
|||
if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
|
||||
return;
|
||||
|
||||
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
|
||||
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
||||
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
|
||||
BUG_ON(!cpg || !clks);
|
||||
BUG_ON(!data || !clks);
|
||||
|
||||
cpg->data.clks = clks;
|
||||
cpg->data.clk_num = num_clks;
|
||||
data->clks = clks;
|
||||
data->clk_num = num_clks;
|
||||
|
||||
cpg->reg = of_iomap(np, 0);
|
||||
base = of_iomap(np, 0);
|
||||
|
||||
for (i = 0; i < num_clks; ++i) {
|
||||
const char *name;
|
||||
|
|
@ -109,15 +106,15 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
|
|||
|
||||
of_property_read_string_index(np, "clock-output-names", i, &name);
|
||||
|
||||
clk = rz_cpg_register_clock(np, cpg, name);
|
||||
clk = rz_cpg_register_clock(np, base, name);
|
||||
if (IS_ERR(clk))
|
||||
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
|
||||
__func__, np, name, PTR_ERR(clk));
|
||||
else
|
||||
cpg->data.clks[i] = clk;
|
||||
data->clks[i] = clk;
|
||||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, data);
|
||||
|
||||
cpg_mstp_add_clk_domain(np);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
struct sh73a0_cpg {
|
||||
struct clk_onecell_data data;
|
||||
spinlock_t lock;
|
||||
void __iomem *reg;
|
||||
};
|
||||
|
||||
#define CPG_FRQCRA 0x00
|
||||
|
|
@ -73,7 +72,7 @@ static const struct clk_div_table z_div_table[] = {
|
|||
|
||||
static struct clk * __init
|
||||
sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
|
||||
const char *name)
|
||||
void __iomem *base, const char *name)
|
||||
{
|
||||
const struct clk_div_table *table = NULL;
|
||||
unsigned int shift, reg, width;
|
||||
|
|
@ -83,12 +82,12 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
|
|||
|
||||
if (!strcmp(name, "main")) {
|
||||
/* extal1, extal1_div2, extal2, extal2_div2 */
|
||||
u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
|
||||
u32 parent_idx = (readl(base + CPG_CKSCR) >> 28) & 3;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
|
||||
div = (parent_idx & 1) + 1;
|
||||
} else if (!strncmp(name, "pll", 3)) {
|
||||
void __iomem *enable_reg = cpg->reg;
|
||||
void __iomem *enable_reg = base;
|
||||
u32 enable_bit = name[3] - '0';
|
||||
|
||||
parent_name = "main";
|
||||
|
|
@ -108,7 +107,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
|
|||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
|
||||
if (readl(base + CPG_PLLECR) & BIT(enable_bit)) {
|
||||
mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
|
||||
/* handle CFG bit for PLL1 and PLL2 */
|
||||
if (enable_bit == 1 || enable_bit == 2)
|
||||
|
|
@ -117,7 +116,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
|
|||
}
|
||||
} else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
|
||||
u32 phy_no = name[3] - '0';
|
||||
void __iomem *dsi_reg = cpg->reg +
|
||||
void __iomem *dsi_reg = base +
|
||||
(phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
|
||||
|
||||
parent_name = phy_no ? "dsi1pck" : "dsi0pck";
|
||||
|
|
@ -154,7 +153,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
|
|||
mult, div);
|
||||
} else {
|
||||
return clk_register_divider_table(NULL, name, parent_name, 0,
|
||||
cpg->reg + reg, shift, width, 0,
|
||||
base + reg, shift, width, 0,
|
||||
table, &cpg->lock);
|
||||
}
|
||||
}
|
||||
|
|
@ -162,6 +161,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
|
|||
static void __init sh73a0_cpg_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct sh73a0_cpg *cpg;
|
||||
void __iomem *base;
|
||||
struct clk **clks;
|
||||
unsigned int i;
|
||||
int num_clks;
|
||||
|
|
@ -186,14 +186,14 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np)
|
|||
cpg->data.clks = clks;
|
||||
cpg->data.clk_num = num_clks;
|
||||
|
||||
cpg->reg = of_iomap(np, 0);
|
||||
if (WARN_ON(cpg->reg == NULL))
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(base == NULL))
|
||||
return;
|
||||
|
||||
/* Set SDHI clocks to a known state */
|
||||
writel(0x108, cpg->reg + CPG_SD0CKCR);
|
||||
writel(0x108, cpg->reg + CPG_SD1CKCR);
|
||||
writel(0x108, cpg->reg + CPG_SD2CKCR);
|
||||
writel(0x108, base + CPG_SD0CKCR);
|
||||
writel(0x108, base + CPG_SD1CKCR);
|
||||
writel(0x108, base + CPG_SD2CKCR);
|
||||
|
||||
for (i = 0; i < num_clks; ++i) {
|
||||
const char *name;
|
||||
|
|
@ -202,7 +202,7 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np)
|
|||
of_property_read_string_index(np, "clock-output-names", i,
|
||||
&name);
|
||||
|
||||
clk = sh73a0_cpg_register_clock(np, cpg, name);
|
||||
clk = sh73a0_cpg_register_clock(np, cpg, base, name);
|
||||
if (IS_ERR(clk))
|
||||
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
|
||||
__func__, np, name, PTR_ERR(clk));
|
||||
|
|
|
|||
|
|
@ -77,6 +77,8 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
|
|||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_GEN4_Z("z0", R8A779F0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
|
||||
DEF_GEN4_Z("z1", R8A779F0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 8),
|
||||
DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1),
|
||||
|
|
@ -118,20 +120,28 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
|
|||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
|
||||
DEF_MOD("hscif0", 514, R8A779F0_CLK_S0D3),
|
||||
DEF_MOD("hscif1", 515, R8A779F0_CLK_S0D3),
|
||||
DEF_MOD("hscif2", 516, R8A779F0_CLK_S0D3),
|
||||
DEF_MOD("hscif3", 517, R8A779F0_CLK_S0D3),
|
||||
DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER),
|
||||
DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER),
|
||||
DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER),
|
||||
DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER),
|
||||
DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER),
|
||||
DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER),
|
||||
DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2),
|
||||
DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2),
|
||||
DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER),
|
||||
DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER),
|
||||
DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER),
|
||||
DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER),
|
||||
DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0),
|
||||
DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
|
||||
DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
|
||||
DEF_MOD("wdt", 907, R8A779F0_CLK_R),
|
||||
DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
|
||||
DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
|
||||
DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC),
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -51,11 +51,9 @@ struct r9a06g032_clkdesc {
|
|||
struct {
|
||||
u16 div, mul;
|
||||
};
|
||||
unsigned int factor;
|
||||
unsigned int frequency;
|
||||
/* for dual gate */
|
||||
struct {
|
||||
uint16_t group : 1, index: 3;
|
||||
uint16_t group : 1;
|
||||
u16 sel, g1, r1, g2, r2;
|
||||
} dual;
|
||||
};
|
||||
|
|
@ -85,10 +83,10 @@ struct r9a06g032_clkdesc {
|
|||
.source = 1 + R9A06G032_##_src, .name = _n, \
|
||||
.reg = _reg, .div_min = _min, .div_max = _max, \
|
||||
.div_table = { __VA_ARGS__ } }
|
||||
#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
|
||||
#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \
|
||||
{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, .name = _n, \
|
||||
.dual = { .group = _g, .index = _gi, \
|
||||
.dual = { .group = _g, \
|
||||
.g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
|
||||
|
||||
enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
|
||||
|
|
@ -290,8 +288,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
|
|||
.name = "uart_group_012",
|
||||
.type = K_BITSEL,
|
||||
.source = 1 + R9A06G032_DIV_UART,
|
||||
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
|
||||
.dual.sel = ((0xec / 4) << 5) | 24,
|
||||
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
|
||||
.dual.sel = ((0x34 / 4) << 5) | 30,
|
||||
.dual.group = 0,
|
||||
},
|
||||
{
|
||||
|
|
@ -299,18 +297,18 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
|
|||
.name = "uart_group_34567",
|
||||
.type = K_BITSEL,
|
||||
.source = 1 + R9A06G032_DIV_P2_PG,
|
||||
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
|
||||
.dual.sel = ((0x34 / 4) << 5) | 30,
|
||||
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
|
||||
.dual.sel = ((0xec / 4) << 5) | 24,
|
||||
.dual.group = 1,
|
||||
},
|
||||
D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
|
||||
D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
|
||||
D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
|
||||
D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763),
|
||||
D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767),
|
||||
D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b),
|
||||
D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f),
|
||||
D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773),
|
||||
D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
|
||||
D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
|
||||
D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
|
||||
D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763),
|
||||
D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767),
|
||||
D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b),
|
||||
D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f),
|
||||
D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773),
|
||||
};
|
||||
|
||||
struct r9a06g032_priv {
|
||||
|
|
|
|||
|
|
@ -36,9 +36,11 @@ enum clk_ids {
|
|||
CLK_PLL3_DIV2_4_2,
|
||||
CLK_SEL_PLL3_3,
|
||||
CLK_DIV_PLL3_C,
|
||||
#ifdef CONFIG_ARM64
|
||||
CLK_PLL5,
|
||||
CLK_PLL5_500,
|
||||
CLK_PLL5_250,
|
||||
#endif
|
||||
CLK_PLL6,
|
||||
CLK_PLL6_250,
|
||||
CLK_P1_DIV2,
|
||||
|
|
@ -100,9 +102,11 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
|
|||
DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
|
||||
DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
|
||||
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
|
||||
#ifdef CONFIG_ARM64
|
||||
DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
|
||||
DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),
|
||||
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),
|
||||
#endif
|
||||
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
|
||||
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
|
||||
|
||||
|
|
@ -126,12 +130,20 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
|
|||
};
|
||||
|
||||
static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
|
||||
#ifdef CONFIG_ARM64
|
||||
DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
|
||||
0x514, 0),
|
||||
DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
|
||||
0x518, 0),
|
||||
DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
|
||||
0x518, 1),
|
||||
#endif
|
||||
#ifdef CONFIG_RISCV
|
||||
DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
|
||||
0x518, 0),
|
||||
DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,
|
||||
0x518, 1),
|
||||
#endif
|
||||
DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
|
||||
0x52c, 0),
|
||||
DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
|
||||
|
|
@ -243,9 +255,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
|
|||
};
|
||||
|
||||
static struct rzg2l_reset r9a07g043_resets[] = {
|
||||
#ifdef CONFIG_ARM64
|
||||
DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
|
||||
DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
|
||||
DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
|
||||
#endif
|
||||
#ifdef CONFIG_RISCV
|
||||
DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
|
||||
#endif
|
||||
DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
|
||||
DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
|
||||
DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
|
||||
|
|
@ -291,8 +308,13 @@ static struct rzg2l_reset r9a07g043_resets[] = {
|
|||
};
|
||||
|
||||
static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
|
||||
#ifdef CONFIG_ARM64
|
||||
MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
|
||||
MOD_CLK_BASE + R9A07G043_IA55_CLK,
|
||||
#endif
|
||||
#ifdef CONFIG_RISCV
|
||||
MOD_CLK_BASE + R9A07G043_IAX45_CLK,
|
||||
#endif
|
||||
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
|
||||
};
|
||||
|
||||
|
|
@ -310,11 +332,21 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = {
|
|||
/* Module Clocks */
|
||||
.mod_clks = r9a07g043_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
|
||||
#ifdef CONFIG_ARM64
|
||||
.num_hw_mod_clks = R9A07G043_TSU_PCLK + 1,
|
||||
#endif
|
||||
#ifdef CONFIG_RISCV
|
||||
.num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1,
|
||||
#endif
|
||||
|
||||
/* Resets */
|
||||
.resets = r9a07g043_resets,
|
||||
#ifdef CONFIG_ARM64
|
||||
.num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */
|
||||
#endif
|
||||
#ifdef CONFIG_RISCV
|
||||
.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
|
||||
#endif
|
||||
|
||||
.has_clk_mon_regs = true,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -182,7 +182,7 @@ static const struct {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct rzg2l_mod_clk common[71];
|
||||
struct rzg2l_mod_clk common[76];
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
struct rzg2l_mod_clk drp[0];
|
||||
#endif
|
||||
|
|
@ -204,6 +204,16 @@ static const struct {
|
|||
0x534, 1),
|
||||
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
|
||||
0x534, 2),
|
||||
DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
|
||||
0x540, 0),
|
||||
DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
|
||||
0x544, 0),
|
||||
DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0,
|
||||
0x544, 1),
|
||||
DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0,
|
||||
0x544, 2),
|
||||
DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0,
|
||||
0x544, 3),
|
||||
DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
|
||||
0x548, 0),
|
||||
DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
|
||||
|
|
@ -346,6 +356,11 @@ static struct rzg2l_reset r9a07g044_resets[] = {
|
|||
DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
|
||||
DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
|
||||
DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
|
||||
DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
|
||||
DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
|
||||
DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
|
||||
DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2),
|
||||
DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
|
||||
DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
|
||||
DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
|
||||
DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
|
||||
|
|
|
|||
|
|
@ -126,19 +126,24 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
|
|||
};
|
||||
|
||||
static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
|
||||
DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
|
||||
DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
|
||||
DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8),
|
||||
DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8),
|
||||
DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
|
||||
DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12),
|
||||
DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12),
|
||||
DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13),
|
||||
DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4),
|
||||
DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
|
||||
DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0),
|
||||
};
|
||||
|
||||
static const struct rzg2l_reset r9a09g011_resets[] = {
|
||||
DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2),
|
||||
DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11),
|
||||
DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
|
||||
DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19),
|
||||
};
|
||||
|
||||
static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
#include "rcar-gen4-cpg.h"
|
||||
#include "rcar-cpg-lib.h"
|
||||
|
||||
static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initconst;
|
||||
static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata;
|
||||
static unsigned int cpg_clk_extalr __initdata;
|
||||
static u32 cpg_mode __initdata;
|
||||
|
||||
|
|
|
|||
|
|
@ -1180,7 +1180,7 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
|
|||
s8 monbit = info->resets[id].monbit;
|
||||
|
||||
if (info->has_clk_mon_regs) {
|
||||
return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
|
||||
return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
|
||||
} else if (monbit >= 0) {
|
||||
u32 monbitmask = BIT(monbit);
|
||||
|
||||
|
|
|
|||
1
include/dt-bindings/clock/qcom,dispcc-sm8350.h
Symbolic link
1
include/dt-bindings/clock/qcom,dispcc-sm8350.h
Symbolic link
|
|
@ -0,0 +1 @@
|
|||
qcom,dispcc-sm8250.h
|
||||
|
|
@ -233,6 +233,7 @@
|
|||
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
|
||||
#define GCC_PCIE0_RCHNG_CLK_SRC 225
|
||||
#define GCC_PCIE0_RCHNG_CLK 226
|
||||
#define GCC_CRYPTO_PPE_CLK 227
|
||||
|
||||
#define GCC_BLSP1_BCR 0
|
||||
#define GCC_BLSP1_QUP1_BCR 1
|
||||
|
|
@ -367,4 +368,7 @@
|
|||
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
|
||||
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
|
||||
|
||||
#define USB0_GDSC 0
|
||||
#define USB1_GDSC 1
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -192,6 +192,7 @@
|
|||
#define GCC_VENUS0_CORE0_VCODEC0_CLK 183
|
||||
#define GCC_VENUS0_CORE1_VCODEC0_CLK 184
|
||||
#define GCC_OXILI_TIMER_CLK 185
|
||||
#define SYSTEM_MM_NOC_BFDCD_CLK_SRC 186
|
||||
|
||||
/* Indexes for GDSCs */
|
||||
#define BIMC_GDSC 0
|
||||
|
|
|
|||
52
include/dt-bindings/clock/qcom,gpucc-sm8350.h
Normal file
52
include/dt-bindings/clock/qcom,gpucc-sm8350.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
|
||||
|
||||
/* GPU_CC clocks */
|
||||
#define GPU_CC_AHB_CLK 0
|
||||
#define GPU_CC_CB_CLK 1
|
||||
#define GPU_CC_CRC_AHB_CLK 2
|
||||
#define GPU_CC_CX_APB_CLK 3
|
||||
#define GPU_CC_CX_GMU_CLK 4
|
||||
#define GPU_CC_CX_QDSS_AT_CLK 5
|
||||
#define GPU_CC_CX_QDSS_TRIG_CLK 6
|
||||
#define GPU_CC_CX_QDSS_TSCTR_CLK 7
|
||||
#define GPU_CC_CX_SNOC_DVM_CLK 8
|
||||
#define GPU_CC_CXO_AON_CLK 9
|
||||
#define GPU_CC_CXO_CLK 10
|
||||
#define GPU_CC_FREQ_MEASURE_CLK 11
|
||||
#define GPU_CC_GMU_CLK_SRC 12
|
||||
#define GPU_CC_GX_GMU_CLK 13
|
||||
#define GPU_CC_GX_QDSS_TSCTR_CLK 14
|
||||
#define GPU_CC_GX_VSENSE_CLK 15
|
||||
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
|
||||
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17
|
||||
#define GPU_CC_HUB_AON_CLK 18
|
||||
#define GPU_CC_HUB_CLK_SRC 19
|
||||
#define GPU_CC_HUB_CX_INT_CLK 20
|
||||
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21
|
||||
#define GPU_CC_MND1X_0_GFX3D_CLK 22
|
||||
#define GPU_CC_MND1X_1_GFX3D_CLK 23
|
||||
#define GPU_CC_PLL0 24
|
||||
#define GPU_CC_PLL1 25
|
||||
#define GPU_CC_SLEEP_CLK 26
|
||||
|
||||
/* GPU_CC resets */
|
||||
#define GPUCC_GPU_CC_ACD_BCR 0
|
||||
#define GPUCC_GPU_CC_CB_BCR 1
|
||||
#define GPUCC_GPU_CC_CX_BCR 2
|
||||
#define GPUCC_GPU_CC_FAST_HUB_BCR 3
|
||||
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
|
||||
#define GPUCC_GPU_CC_GMU_BCR 5
|
||||
#define GPUCC_GPU_CC_GX_BCR 6
|
||||
#define GPUCC_GPU_CC_XO_BCR 7
|
||||
|
||||
/* GPU_CC GDSCRs */
|
||||
#define GPU_CX_GDSC 0
|
||||
#define GPU_GX_GDSC 1
|
||||
|
||||
#endif
|
||||
159
include/dt-bindings/clock/qcom,sm8450-camcc.h
Normal file
159
include/dt-bindings/clock/qcom,sm8450-camcc.h
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H
|
||||
|
||||
/* CAM_CC clocks */
|
||||
#define CAM_CC_BPS_AHB_CLK 0
|
||||
#define CAM_CC_BPS_CLK 1
|
||||
#define CAM_CC_BPS_CLK_SRC 2
|
||||
#define CAM_CC_BPS_FAST_AHB_CLK 3
|
||||
#define CAM_CC_CAMNOC_AXI_CLK 4
|
||||
#define CAM_CC_CAMNOC_AXI_CLK_SRC 5
|
||||
#define CAM_CC_CAMNOC_DCD_XO_CLK 6
|
||||
#define CAM_CC_CCI_0_CLK 7
|
||||
#define CAM_CC_CCI_0_CLK_SRC 8
|
||||
#define CAM_CC_CCI_1_CLK 9
|
||||
#define CAM_CC_CCI_1_CLK_SRC 10
|
||||
#define CAM_CC_CORE_AHB_CLK 11
|
||||
#define CAM_CC_CPAS_AHB_CLK 12
|
||||
#define CAM_CC_CPAS_BPS_CLK 13
|
||||
#define CAM_CC_CPAS_FAST_AHB_CLK 14
|
||||
#define CAM_CC_CPAS_IFE_0_CLK 15
|
||||
#define CAM_CC_CPAS_IFE_1_CLK 16
|
||||
#define CAM_CC_CPAS_IFE_2_CLK 17
|
||||
#define CAM_CC_CPAS_IFE_LITE_CLK 18
|
||||
#define CAM_CC_CPAS_IPE_NPS_CLK 19
|
||||
#define CAM_CC_CPAS_SBI_CLK 20
|
||||
#define CAM_CC_CPAS_SFE_0_CLK 21
|
||||
#define CAM_CC_CPAS_SFE_1_CLK 22
|
||||
#define CAM_CC_CPHY_RX_CLK_SRC 23
|
||||
#define CAM_CC_CSI0PHYTIMER_CLK 24
|
||||
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 25
|
||||
#define CAM_CC_CSI1PHYTIMER_CLK 26
|
||||
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 27
|
||||
#define CAM_CC_CSI2PHYTIMER_CLK 28
|
||||
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 29
|
||||
#define CAM_CC_CSI3PHYTIMER_CLK 30
|
||||
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 31
|
||||
#define CAM_CC_CSI4PHYTIMER_CLK 32
|
||||
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 33
|
||||
#define CAM_CC_CSI5PHYTIMER_CLK 34
|
||||
#define CAM_CC_CSI5PHYTIMER_CLK_SRC 35
|
||||
#define CAM_CC_CSID_CLK 36
|
||||
#define CAM_CC_CSID_CLK_SRC 37
|
||||
#define CAM_CC_CSID_CSIPHY_RX_CLK 38
|
||||
#define CAM_CC_CSIPHY0_CLK 39
|
||||
#define CAM_CC_CSIPHY1_CLK 40
|
||||
#define CAM_CC_CSIPHY2_CLK 41
|
||||
#define CAM_CC_CSIPHY3_CLK 42
|
||||
#define CAM_CC_CSIPHY4_CLK 43
|
||||
#define CAM_CC_CSIPHY5_CLK 44
|
||||
#define CAM_CC_FAST_AHB_CLK_SRC 45
|
||||
#define CAM_CC_GDSC_CLK 46
|
||||
#define CAM_CC_ICP_AHB_CLK 47
|
||||
#define CAM_CC_ICP_CLK 48
|
||||
#define CAM_CC_ICP_CLK_SRC 49
|
||||
#define CAM_CC_IFE_0_CLK 50
|
||||
#define CAM_CC_IFE_0_CLK_SRC 51
|
||||
#define CAM_CC_IFE_0_DSP_CLK 52
|
||||
#define CAM_CC_IFE_0_FAST_AHB_CLK 53
|
||||
#define CAM_CC_IFE_1_CLK 54
|
||||
#define CAM_CC_IFE_1_CLK_SRC 55
|
||||
#define CAM_CC_IFE_1_DSP_CLK 56
|
||||
#define CAM_CC_IFE_1_FAST_AHB_CLK 57
|
||||
#define CAM_CC_IFE_2_CLK 58
|
||||
#define CAM_CC_IFE_2_CLK_SRC 59
|
||||
#define CAM_CC_IFE_2_DSP_CLK 60
|
||||
#define CAM_CC_IFE_2_FAST_AHB_CLK 61
|
||||
#define CAM_CC_IFE_LITE_AHB_CLK 62
|
||||
#define CAM_CC_IFE_LITE_CLK 63
|
||||
#define CAM_CC_IFE_LITE_CLK_SRC 64
|
||||
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 65
|
||||
#define CAM_CC_IFE_LITE_CSID_CLK 66
|
||||
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 67
|
||||
#define CAM_CC_IPE_NPS_AHB_CLK 68
|
||||
#define CAM_CC_IPE_NPS_CLK 69
|
||||
#define CAM_CC_IPE_NPS_CLK_SRC 70
|
||||
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 71
|
||||
#define CAM_CC_IPE_PPS_CLK 72
|
||||
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 73
|
||||
#define CAM_CC_JPEG_CLK 74
|
||||
#define CAM_CC_JPEG_CLK_SRC 75
|
||||
#define CAM_CC_MCLK0_CLK 76
|
||||
#define CAM_CC_MCLK0_CLK_SRC 77
|
||||
#define CAM_CC_MCLK1_CLK 78
|
||||
#define CAM_CC_MCLK1_CLK_SRC 79
|
||||
#define CAM_CC_MCLK2_CLK 80
|
||||
#define CAM_CC_MCLK2_CLK_SRC 81
|
||||
#define CAM_CC_MCLK3_CLK 82
|
||||
#define CAM_CC_MCLK3_CLK_SRC 83
|
||||
#define CAM_CC_MCLK4_CLK 84
|
||||
#define CAM_CC_MCLK4_CLK_SRC 85
|
||||
#define CAM_CC_MCLK5_CLK 86
|
||||
#define CAM_CC_MCLK5_CLK_SRC 87
|
||||
#define CAM_CC_MCLK6_CLK 88
|
||||
#define CAM_CC_MCLK6_CLK_SRC 89
|
||||
#define CAM_CC_MCLK7_CLK 90
|
||||
#define CAM_CC_MCLK7_CLK_SRC 91
|
||||
#define CAM_CC_PLL0 92
|
||||
#define CAM_CC_PLL0_OUT_EVEN 93
|
||||
#define CAM_CC_PLL0_OUT_ODD 94
|
||||
#define CAM_CC_PLL1 95
|
||||
#define CAM_CC_PLL1_OUT_EVEN 96
|
||||
#define CAM_CC_PLL2 97
|
||||
#define CAM_CC_PLL3 98
|
||||
#define CAM_CC_PLL3_OUT_EVEN 99
|
||||
#define CAM_CC_PLL4 100
|
||||
#define CAM_CC_PLL4_OUT_EVEN 101
|
||||
#define CAM_CC_PLL5 102
|
||||
#define CAM_CC_PLL5_OUT_EVEN 103
|
||||
#define CAM_CC_PLL6 104
|
||||
#define CAM_CC_PLL6_OUT_EVEN 105
|
||||
#define CAM_CC_PLL7 106
|
||||
#define CAM_CC_PLL7_OUT_EVEN 107
|
||||
#define CAM_CC_PLL8 108
|
||||
#define CAM_CC_PLL8_OUT_EVEN 109
|
||||
#define CAM_CC_QDSS_DEBUG_CLK 110
|
||||
#define CAM_CC_QDSS_DEBUG_CLK_SRC 111
|
||||
#define CAM_CC_QDSS_DEBUG_XO_CLK 112
|
||||
#define CAM_CC_SBI_AHB_CLK 113
|
||||
#define CAM_CC_SBI_CLK 114
|
||||
#define CAM_CC_SFE_0_CLK 115
|
||||
#define CAM_CC_SFE_0_CLK_SRC 116
|
||||
#define CAM_CC_SFE_0_FAST_AHB_CLK 117
|
||||
#define CAM_CC_SFE_1_CLK 118
|
||||
#define CAM_CC_SFE_1_CLK_SRC 119
|
||||
#define CAM_CC_SFE_1_FAST_AHB_CLK 120
|
||||
#define CAM_CC_SLEEP_CLK 121
|
||||
#define CAM_CC_SLEEP_CLK_SRC 122
|
||||
#define CAM_CC_SLOW_AHB_CLK_SRC 123
|
||||
#define CAM_CC_XO_CLK_SRC 124
|
||||
|
||||
/* CAM_CC resets */
|
||||
#define CAM_CC_BPS_BCR 0
|
||||
#define CAM_CC_ICP_BCR 1
|
||||
#define CAM_CC_IFE_0_BCR 2
|
||||
#define CAM_CC_IFE_1_BCR 3
|
||||
#define CAM_CC_IFE_2_BCR 4
|
||||
#define CAM_CC_IPE_0_BCR 5
|
||||
#define CAM_CC_QDSS_DEBUG_BCR 6
|
||||
#define CAM_CC_SBI_BCR 7
|
||||
#define CAM_CC_SFE_0_BCR 8
|
||||
#define CAM_CC_SFE_1_BCR 9
|
||||
|
||||
/* CAM_CC GDSCRs */
|
||||
#define BPS_GDSC 0
|
||||
#define IPE_0_GDSC 1
|
||||
#define SBI_GDSC 2
|
||||
#define IFE_0_GDSC 3
|
||||
#define IFE_1_GDSC 4
|
||||
#define IFE_2_GDSC 5
|
||||
#define SFE_0_GDSC 6
|
||||
#define SFE_1_GDSC 7
|
||||
#define TITAN_TOP_GDSC 8
|
||||
|
||||
#endif
|
||||
|
|
@ -108,6 +108,15 @@
|
|||
#define R9A07G043_ADC_ADCLK 76
|
||||
#define R9A07G043_ADC_PCLK 77
|
||||
#define R9A07G043_TSU_PCLK 78
|
||||
#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */
|
||||
#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */
|
||||
#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */
|
||||
#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */
|
||||
#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */
|
||||
#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */
|
||||
#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */
|
||||
#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */
|
||||
#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */
|
||||
|
||||
/* R9A07G043 Resets */
|
||||
#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */
|
||||
|
|
@ -180,5 +189,16 @@
|
|||
#define R9A07G043_ADC_PRESETN 67
|
||||
#define R9A07G043_ADC_ADRST_N 68
|
||||
#define R9A07G043_TSU_PRESETN 69
|
||||
#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */
|
||||
#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */
|
||||
#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */
|
||||
#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */
|
||||
#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */
|
||||
#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */
|
||||
#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */
|
||||
#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */
|
||||
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
|
||||
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
|
||||
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
|
||||
|
|
|
|||
397
include/dt-bindings/clock/sprd,ums512-clk.h
Normal file
397
include/dt-bindings/clock/sprd,ums512-clk.h
Normal file
|
|
@ -0,0 +1,397 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Unisoc UMS512 SoC DTS file
|
||||
*
|
||||
* Copyright (C) 2022, Unisoc Inc.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_UMS512_H_
|
||||
#define _DT_BINDINGS_CLK_UMS512_H_
|
||||
|
||||
#define CLK_26M_AUD 0
|
||||
#define CLK_13M 1
|
||||
#define CLK_6M5 2
|
||||
#define CLK_4M3 3
|
||||
#define CLK_2M 4
|
||||
#define CLK_1M 5
|
||||
#define CLK_250K 6
|
||||
#define CLK_RCO_25M 7
|
||||
#define CLK_RCO_4M 8
|
||||
#define CLK_RCO_2M 9
|
||||
#define CLK_ISPPLL_GATE 10
|
||||
#define CLK_DPLL0_GATE 11
|
||||
#define CLK_DPLL1_GATE 12
|
||||
#define CLK_LPLL_GATE 13
|
||||
#define CLK_TWPLL_GATE 14
|
||||
#define CLK_GPLL_GATE 15
|
||||
#define CLK_RPLL_GATE 16
|
||||
#define CLK_CPPLL_GATE 17
|
||||
#define CLK_MPLL0_GATE 18
|
||||
#define CLK_MPLL1_GATE 19
|
||||
#define CLK_MPLL2_GATE 20
|
||||
#define CLK_PMU_GATE_NUM (CLK_MPLL2_GATE + 1)
|
||||
|
||||
#define CLK_DPLL0 0
|
||||
#define CLK_DPLL0_58M31 1
|
||||
#define CLK_ANLG_PHY_G0_NUM (CLK_DPLL0_58M31 + 1)
|
||||
|
||||
#define CLK_MPLL1 0
|
||||
#define CLK_MPLL1_63M38 1
|
||||
#define CLK_ANLG_PHY_G2_NUM (CLK_MPLL1_63M38 + 1)
|
||||
|
||||
#define CLK_RPLL 0
|
||||
#define CLK_AUDIO_GATE 1
|
||||
#define CLK_MPLL0 2
|
||||
#define CLK_MPLL0_56M88 3
|
||||
#define CLK_MPLL2 4
|
||||
#define CLK_MPLL2_47M13 5
|
||||
#define CLK_ANLG_PHY_G3_NUM (CLK_MPLL2_47M13 + 1)
|
||||
|
||||
#define CLK_TWPLL 0
|
||||
#define CLK_TWPLL_768M 1
|
||||
#define CLK_TWPLL_384M 2
|
||||
#define CLK_TWPLL_192M 3
|
||||
#define CLK_TWPLL_96M 4
|
||||
#define CLK_TWPLL_48M 5
|
||||
#define CLK_TWPLL_24M 6
|
||||
#define CLK_TWPLL_12M 7
|
||||
#define CLK_TWPLL_512M 8
|
||||
#define CLK_TWPLL_256M 9
|
||||
#define CLK_TWPLL_128M 10
|
||||
#define CLK_TWPLL_64M 11
|
||||
#define CLK_TWPLL_307M2 12
|
||||
#define CLK_TWPLL_219M4 13
|
||||
#define CLK_TWPLL_170M6 14
|
||||
#define CLK_TWPLL_153M6 15
|
||||
#define CLK_TWPLL_76M8 16
|
||||
#define CLK_TWPLL_51M2 17
|
||||
#define CLK_TWPLL_38M4 18
|
||||
#define CLK_TWPLL_19M2 19
|
||||
#define CLK_TWPLL_12M29 20
|
||||
#define CLK_LPLL 21
|
||||
#define CLK_LPLL_614M4 22
|
||||
#define CLK_LPLL_409M6 23
|
||||
#define CLK_LPLL_245M76 24
|
||||
#define CLK_LPLL_30M72 25
|
||||
#define CLK_ISPPLL 26
|
||||
#define CLK_ISPPLL_468M 27
|
||||
#define CLK_ISPPLL_78M 28
|
||||
#define CLK_GPLL 29
|
||||
#define CLK_GPLL_40M 30
|
||||
#define CLK_CPPLL 31
|
||||
#define CLK_CPPLL_39M32 32
|
||||
#define CLK_ANLG_PHY_GC_NUM (CLK_CPPLL_39M32 + 1)
|
||||
|
||||
#define CLK_AP_APB 0
|
||||
#define CLK_IPI 1
|
||||
#define CLK_AP_UART0 2
|
||||
#define CLK_AP_UART1 3
|
||||
#define CLK_AP_UART2 4
|
||||
#define CLK_AP_I2C0 5
|
||||
#define CLK_AP_I2C1 6
|
||||
#define CLK_AP_I2C2 7
|
||||
#define CLK_AP_I2C3 8
|
||||
#define CLK_AP_I2C4 9
|
||||
#define CLK_AP_SPI0 10
|
||||
#define CLK_AP_SPI1 11
|
||||
#define CLK_AP_SPI2 12
|
||||
#define CLK_AP_SPI3 13
|
||||
#define CLK_AP_IIS0 14
|
||||
#define CLK_AP_IIS1 15
|
||||
#define CLK_AP_IIS2 16
|
||||
#define CLK_AP_SIM 17
|
||||
#define CLK_AP_CE 18
|
||||
#define CLK_SDIO0_2X 19
|
||||
#define CLK_SDIO1_2X 20
|
||||
#define CLK_EMMC_2X 21
|
||||
#define CLK_VSP 22
|
||||
#define CLK_DISPC0 23
|
||||
#define CLK_DISPC0_DPI 24
|
||||
#define CLK_DSI_APB 25
|
||||
#define CLK_DSI_RXESC 26
|
||||
#define CLK_DSI_LANEBYTE 27
|
||||
#define CLK_VDSP 28
|
||||
#define CLK_VDSP_M 29
|
||||
#define CLK_AP_CLK_NUM (CLK_VDSP_M + 1)
|
||||
|
||||
#define CLK_DSI_EB 0
|
||||
#define CLK_DISPC_EB 1
|
||||
#define CLK_VSP_EB 2
|
||||
#define CLK_VDMA_EB 3
|
||||
#define CLK_DMA_PUB_EB 4
|
||||
#define CLK_DMA_SEC_EB 5
|
||||
#define CLK_IPI_EB 6
|
||||
#define CLK_AHB_CKG_EB 7
|
||||
#define CLK_BM_CLK_EB 8
|
||||
#define CLK_AP_AHB_GATE_NUM (CLK_BM_CLK_EB + 1)
|
||||
|
||||
#define CLK_AON_APB 0
|
||||
#define CLK_ADI 1
|
||||
#define CLK_AUX0 2
|
||||
#define CLK_AUX1 3
|
||||
#define CLK_AUX2 4
|
||||
#define CLK_PROBE 5
|
||||
#define CLK_PWM0 6
|
||||
#define CLK_PWM1 7
|
||||
#define CLK_PWM2 8
|
||||
#define CLK_PWM3 9
|
||||
#define CLK_EFUSE 10
|
||||
#define CLK_UART0 11
|
||||
#define CLK_UART1 12
|
||||
#define CLK_THM0 13
|
||||
#define CLK_THM1 14
|
||||
#define CLK_THM2 15
|
||||
#define CLK_THM3 16
|
||||
#define CLK_AON_I2C 17
|
||||
#define CLK_AON_IIS 18
|
||||
#define CLK_SCC 19
|
||||
#define CLK_APCPU_DAP 20
|
||||
#define CLK_APCPU_DAP_MTCK 21
|
||||
#define CLK_APCPU_TS 22
|
||||
#define CLK_DEBUG_TS 23
|
||||
#define CLK_DSI_TEST_S 24
|
||||
#define CLK_DJTAG_TCK 25
|
||||
#define CLK_DJTAG_TCK_HW 26
|
||||
#define CLK_AON_TMR 27
|
||||
#define CLK_AON_PMU 28
|
||||
#define CLK_DEBOUNCE 29
|
||||
#define CLK_APCPU_PMU 30
|
||||
#define CLK_TOP_DVFS 31
|
||||
#define CLK_OTG_UTMI 32
|
||||
#define CLK_OTG_REF 33
|
||||
#define CLK_CSSYS 34
|
||||
#define CLK_CSSYS_PUB 35
|
||||
#define CLK_CSSYS_APB 36
|
||||
#define CLK_AP_AXI 37
|
||||
#define CLK_AP_MM 38
|
||||
#define CLK_SDIO2_2X 39
|
||||
#define CLK_ANALOG_IO_APB 40
|
||||
#define CLK_DMC_REF_CLK 41
|
||||
#define CLK_EMC 42
|
||||
#define CLK_USB 43
|
||||
#define CLK_26M_PMU 44
|
||||
#define CLK_AON_APB_NUM (CLK_26M_PMU + 1)
|
||||
|
||||
#define CLK_MM_AHB 0
|
||||
#define CLK_MM_MTX 1
|
||||
#define CLK_SENSOR0 2
|
||||
#define CLK_SENSOR1 3
|
||||
#define CLK_SENSOR2 4
|
||||
#define CLK_CPP 5
|
||||
#define CLK_JPG 6
|
||||
#define CLK_FD 7
|
||||
#define CLK_DCAM_IF 8
|
||||
#define CLK_DCAM_AXI 9
|
||||
#define CLK_ISP 10
|
||||
#define CLK_MIPI_CSI0 11
|
||||
#define CLK_MIPI_CSI1 12
|
||||
#define CLK_MIPI_CSI2 13
|
||||
#define CLK_MM_CLK_NUM (CLK_MIPI_CSI2 + 1)
|
||||
|
||||
#define CLK_RC100M_CAL_EB 0
|
||||
#define CLK_DJTAG_TCK_EB 1
|
||||
#define CLK_DJTAG_EB 2
|
||||
#define CLK_AUX0_EB 3
|
||||
#define CLK_AUX1_EB 4
|
||||
#define CLK_AUX2_EB 5
|
||||
#define CLK_PROBE_EB 6
|
||||
#define CLK_MM_EB 7
|
||||
#define CLK_GPU_EB 8
|
||||
#define CLK_MSPI_EB 9
|
||||
#define CLK_APCPU_DAP_EB 10
|
||||
#define CLK_AON_CSSYS_EB 11
|
||||
#define CLK_CSSYS_APB_EB 12
|
||||
#define CLK_CSSYS_PUB_EB 13
|
||||
#define CLK_SDPHY_CFG_EB 14
|
||||
#define CLK_SDPHY_REF_EB 15
|
||||
#define CLK_EFUSE_EB 16
|
||||
#define CLK_GPIO_EB 17
|
||||
#define CLK_MBOX_EB 18
|
||||
#define CLK_KPD_EB 19
|
||||
#define CLK_AON_SYST_EB 20
|
||||
#define CLK_AP_SYST_EB 21
|
||||
#define CLK_AON_TMR_EB 22
|
||||
#define CLK_OTG_UTMI_EB 23
|
||||
#define CLK_OTG_PHY_EB 24
|
||||
#define CLK_SPLK_EB 25
|
||||
#define CLK_PIN_EB 26
|
||||
#define CLK_ANA_EB 27
|
||||
#define CLK_APCPU_TS0_EB 28
|
||||
#define CLK_APB_BUSMON_EB 29
|
||||
#define CLK_AON_IIS_EB 30
|
||||
#define CLK_SCC_EB 31
|
||||
#define CLK_THM0_EB 32
|
||||
#define CLK_THM1_EB 33
|
||||
#define CLK_THM2_EB 34
|
||||
#define CLK_ASIM_TOP_EB 35
|
||||
#define CLK_I2C_EB 36
|
||||
#define CLK_PMU_EB 37
|
||||
#define CLK_ADI_EB 38
|
||||
#define CLK_EIC_EB 39
|
||||
#define CLK_AP_INTC0_EB 40
|
||||
#define CLK_AP_INTC1_EB 41
|
||||
#define CLK_AP_INTC2_EB 42
|
||||
#define CLK_AP_INTC3_EB 43
|
||||
#define CLK_AP_INTC4_EB 44
|
||||
#define CLK_AP_INTC5_EB 45
|
||||
#define CLK_AUDCP_INTC_EB 46
|
||||
#define CLK_AP_TMR0_EB 47
|
||||
#define CLK_AP_TMR1_EB 48
|
||||
#define CLK_AP_TMR2_EB 49
|
||||
#define CLK_PWM0_EB 50
|
||||
#define CLK_PWM1_EB 51
|
||||
#define CLK_PWM2_EB 52
|
||||
#define CLK_PWM3_EB 53
|
||||
#define CLK_AP_WDG_EB 54
|
||||
#define CLK_APCPU_WDG_EB 55
|
||||
#define CLK_SERDES_EB 56
|
||||
#define CLK_ARCH_RTC_EB 57
|
||||
#define CLK_KPD_RTC_EB 58
|
||||
#define CLK_AON_SYST_RTC_EB 59
|
||||
#define CLK_AP_SYST_RTC_EB 60
|
||||
#define CLK_AON_TMR_RTC_EB 61
|
||||
#define CLK_EIC_RTC_EB 62
|
||||
#define CLK_EIC_RTCDV5_EB 63
|
||||
#define CLK_AP_WDG_RTC_EB 64
|
||||
#define CLK_AC_WDG_RTC_EB 65
|
||||
#define CLK_AP_TMR0_RTC_EB 66
|
||||
#define CLK_AP_TMR1_RTC_EB 67
|
||||
#define CLK_AP_TMR2_RTC_EB 68
|
||||
#define CLK_DCXO_LC_RTC_EB 69
|
||||
#define CLK_BB_CAL_RTC_EB 70
|
||||
#define CLK_AP_EMMC_RTC_EB 71
|
||||
#define CLK_AP_SDIO0_RTC_EB 72
|
||||
#define CLK_AP_SDIO1_RTC_EB 73
|
||||
#define CLK_AP_SDIO2_RTC_EB 74
|
||||
#define CLK_DSI_CSI_TEST_EB 75
|
||||
#define CLK_DJTAG_TCK_EN 76
|
||||
#define CLK_DPHY_REF_EB 77
|
||||
#define CLK_DMC_REF_EB 78
|
||||
#define CLK_OTG_REF_EB 79
|
||||
#define CLK_TSEN_EB 80
|
||||
#define CLK_TMR_EB 81
|
||||
#define CLK_RC100M_REF_EB 82
|
||||
#define CLK_RC100M_FDK_EB 83
|
||||
#define CLK_DEBOUNCE_EB 84
|
||||
#define CLK_DET_32K_EB 85
|
||||
#define CLK_TOP_CSSYS_EB 86
|
||||
#define CLK_AP_AXI_EN 87
|
||||
#define CLK_SDIO0_2X_EN 88
|
||||
#define CLK_SDIO0_1X_EN 89
|
||||
#define CLK_SDIO1_2X_EN 90
|
||||
#define CLK_SDIO1_1X_EN 91
|
||||
#define CLK_SDIO2_2X_EN 92
|
||||
#define CLK_SDIO2_1X_EN 93
|
||||
#define CLK_EMMC_2X_EN 94
|
||||
#define CLK_EMMC_1X_EN 95
|
||||
#define CLK_PLL_TEST_EN 96
|
||||
#define CLK_CPHY_CFG_EN 97
|
||||
#define CLK_DEBUG_TS_EN 98
|
||||
#define CLK_ACCESS_AUD_EN 99
|
||||
#define CLK_AON_APB_GATE_NUM (CLK_ACCESS_AUD_EN + 1)
|
||||
|
||||
#define CLK_MM_CPP_EB 0
|
||||
#define CLK_MM_JPG_EB 1
|
||||
#define CLK_MM_DCAM_EB 2
|
||||
#define CLK_MM_ISP_EB 3
|
||||
#define CLK_MM_CSI2_EB 4
|
||||
#define CLK_MM_CSI1_EB 5
|
||||
#define CLK_MM_CSI0_EB 6
|
||||
#define CLK_MM_CKG_EB 7
|
||||
#define CLK_ISP_AHB_EB 8
|
||||
#define CLK_MM_DVFS_EB 9
|
||||
#define CLK_MM_FD_EB 10
|
||||
#define CLK_MM_SENSOR2_EB 11
|
||||
#define CLK_MM_SENSOR1_EB 12
|
||||
#define CLK_MM_SENSOR0_EB 13
|
||||
#define CLK_MM_MIPI_CSI2_EB 14
|
||||
#define CLK_MM_MIPI_CSI1_EB 15
|
||||
#define CLK_MM_MIPI_CSI0_EB 16
|
||||
#define CLK_DCAM_AXI_EB 17
|
||||
#define CLK_ISP_AXI_EB 18
|
||||
#define CLK_MM_CPHY_EB 19
|
||||
#define CLK_MM_GATE_CLK_NUM (CLK_MM_CPHY_EB + 1)
|
||||
|
||||
#define CLK_SIM0_EB 0
|
||||
#define CLK_IIS0_EB 1
|
||||
#define CLK_IIS1_EB 2
|
||||
#define CLK_IIS2_EB 3
|
||||
#define CLK_APB_REG_EB 4
|
||||
#define CLK_SPI0_EB 5
|
||||
#define CLK_SPI1_EB 6
|
||||
#define CLK_SPI2_EB 7
|
||||
#define CLK_SPI3_EB 8
|
||||
#define CLK_I2C0_EB 9
|
||||
#define CLK_I2C1_EB 10
|
||||
#define CLK_I2C2_EB 11
|
||||
#define CLK_I2C3_EB 12
|
||||
#define CLK_I2C4_EB 13
|
||||
#define CLK_UART0_EB 14
|
||||
#define CLK_UART1_EB 15
|
||||
#define CLK_UART2_EB 16
|
||||
#define CLK_SIM0_32K_EB 17
|
||||
#define CLK_SPI0_LFIN_EB 18
|
||||
#define CLK_SPI1_LFIN_EB 19
|
||||
#define CLK_SPI2_LFIN_EB 20
|
||||
#define CLK_SPI3_LFIN_EB 21
|
||||
#define CLK_SDIO0_EB 22
|
||||
#define CLK_SDIO1_EB 23
|
||||
#define CLK_SDIO2_EB 24
|
||||
#define CLK_EMMC_EB 25
|
||||
#define CLK_SDIO0_32K_EB 26
|
||||
#define CLK_SDIO1_32K_EB 27
|
||||
#define CLK_SDIO2_32K_EB 28
|
||||
#define CLK_EMMC_32K_EB 29
|
||||
#define CLK_AP_APB_GATE_NUM (CLK_EMMC_32K_EB + 1)
|
||||
|
||||
#define CLK_GPU_CORE_EB 0
|
||||
#define CLK_GPU_CORE 1
|
||||
#define CLK_GPU_MEM_EB 2
|
||||
#define CLK_GPU_MEM 3
|
||||
#define CLK_GPU_SYS_EB 4
|
||||
#define CLK_GPU_SYS 5
|
||||
#define CLK_GPU_CLK_NUM (CLK_GPU_SYS + 1)
|
||||
|
||||
#define CLK_AUDCP_IIS0_EB 0
|
||||
#define CLK_AUDCP_IIS1_EB 1
|
||||
#define CLK_AUDCP_IIS2_EB 2
|
||||
#define CLK_AUDCP_UART_EB 3
|
||||
#define CLK_AUDCP_DMA_CP_EB 4
|
||||
#define CLK_AUDCP_DMA_AP_EB 5
|
||||
#define CLK_AUDCP_SRC48K_EB 6
|
||||
#define CLK_AUDCP_MCDT_EB 7
|
||||
#define CLK_AUDCP_VBCIFD_EB 8
|
||||
#define CLK_AUDCP_VBC_EB 9
|
||||
#define CLK_AUDCP_SPLK_EB 10
|
||||
#define CLK_AUDCP_ICU_EB 11
|
||||
#define CLK_AUDCP_DMA_AP_ASHB_EB 12
|
||||
#define CLK_AUDCP_DMA_CP_ASHB_EB 13
|
||||
#define CLK_AUDCP_AUD_EB 14
|
||||
#define CLK_AUDCP_VBC_24M_EB 15
|
||||
#define CLK_AUDCP_TMR_26M_EB 16
|
||||
#define CLK_AUDCP_DVFS_ASHB_EB 17
|
||||
#define CLK_AUDCP_AHB_GATE_NUM (CLK_AUDCP_DVFS_ASHB_EB + 1)
|
||||
|
||||
#define CLK_AUDCP_WDG_EB 0
|
||||
#define CLK_AUDCP_RTC_WDG_EB 1
|
||||
#define CLK_AUDCP_TMR0_EB 2
|
||||
#define CLK_AUDCP_TMR1_EB 3
|
||||
#define CLK_AUDCP_APB_GATE_NUM (CLK_AUDCP_TMR1_EB + 1)
|
||||
|
||||
#define CLK_ACORE0 0
|
||||
#define CLK_ACORE1 1
|
||||
#define CLK_ACORE2 2
|
||||
#define CLK_ACORE3 3
|
||||
#define CLK_ACORE4 4
|
||||
#define CLK_ACORE5 5
|
||||
#define CLK_PCORE0 6
|
||||
#define CLK_PCORE1 7
|
||||
#define CLK_SCU 8
|
||||
#define CLK_ACE 9
|
||||
#define CLK_PERIPH 10
|
||||
#define CLK_GIC 11
|
||||
#define CLK_ATB 12
|
||||
#define CLK_DEBUG_APB 13
|
||||
#define CLK_APCPU_SEC_NUM (CLK_DEBUG_APB + 1)
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_UMS512_H_ */
|
||||
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Reference in a new issue