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clk: agilex/stratix10/n5x: fix how the bypass_reg is handled
If the bypass_reg is set, then we can return the bypass parent, however,
if there is not a bypass_reg, we need to figure what the correct parent
mux is.
The previous code never handled the parent mux if there was a
bypass_reg.
Fixes: 80c6b7a089
("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210611025201.118799-4-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
c2c9c5661a
commit
dfd1427c37
1 changed files with 8 additions and 3 deletions
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@ -64,16 +64,21 @@ static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
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{
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struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
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u32 clk_src, mask;
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u8 parent;
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u8 parent = 0;
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/* handle the bypass first */
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if (socfpgaclk->bypass_reg) {
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mask = (0x1 << socfpgaclk->bypass_shift);
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parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
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socfpgaclk->bypass_shift);
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} else {
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if (parent)
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return parent;
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}
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if (socfpgaclk->hw.reg) {
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clk_src = readl(socfpgaclk->hw.reg);
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parent = (clk_src >> CLK_MGR_FREE_SHIFT) &
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CLK_MGR_FREE_MASK;
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CLK_MGR_FREE_MASK;
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}
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return parent;
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}
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