arm64: dts: imx8: conn: fix enet clock setting
enet_clk_ref actually is sourced from internal gpr clocks which needs a default rate. Also update enet lpcg clock output names to be more straightforward. Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -77,9 +77,12 @@ conn_subsys: bus@5b000000 {
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
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<&enet0_lpcg IMX_LPCG_CLK_2>,
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<&enet0_lpcg IMX_LPCG_CLK_1>,
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<&enet0_lpcg IMX_LPCG_CLK_3>,
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<&enet0_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
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assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
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assigned-clock-rates = <250000000>, <125000000>;
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fsl,num-tx-queues=<3>;
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fsl,num-rx-queues=<3>;
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power-domains = <&pd IMX_SC_R_ENET_0>;
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@ -94,9 +97,12 @@ conn_subsys: bus@5b000000 {
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<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
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<&enet1_lpcg IMX_LPCG_CLK_2>,
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<&enet1_lpcg IMX_LPCG_CLK_1>,
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<&enet1_lpcg IMX_LPCG_CLK_3>,
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<&enet1_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
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assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
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assigned-clock-rates = <250000000>, <125000000>;
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fsl,num-tx-queues=<3>;
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fsl,num-rx-queues=<3>;
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power-domains = <&pd IMX_SC_R_ENET_1>;
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@ -152,15 +158,19 @@ conn_subsys: bus@5b000000 {
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
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<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
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<&conn_axi_clk>,
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<&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
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<&conn_ipg_clk>,
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<&conn_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
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<IMX_LPCG_CLK_5>;
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clock-output-names = "enet0_ipg_root_clk",
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"enet0_tx_clk",
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"enet0_ahb_clk",
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"enet0_ipg_clk",
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"enet0_ipg_s_clk";
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
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clock-output-names = "enet0_lpcg_timer_clk",
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"enet0_lpcg_txc_sampling_clk",
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"enet0_lpcg_ahb_clk",
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"enet0_lpcg_rgmii_txc_clk",
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"enet0_lpcg_ipg_clk",
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"enet0_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_ENET_0>;
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};
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@ -170,15 +180,19 @@ conn_subsys: bus@5b000000 {
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
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<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
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<&conn_axi_clk>,
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<&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
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<&conn_ipg_clk>,
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<&conn_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
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<IMX_LPCG_CLK_5>;
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clock-output-names = "enet1_ipg_root_clk",
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"enet1_tx_clk",
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"enet1_ahb_clk",
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"enet1_ipg_clk",
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"enet1_ipg_s_clk";
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
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clock-output-names = "enet1_lpcg_timer_clk",
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"enet1_lpcg_txc_sampling_clk",
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"enet1_lpcg_ahb_clk",
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"enet1_lpcg_rgmii_txc_clk",
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"enet1_lpcg_ipg_clk",
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"enet1_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_ENET_1>;
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};
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};
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