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i2c-s3c2410: Fix I2C SDA to SCL setup time
Fix the setup time for SDA to SCL due to the way the S3C24XX I2C controller works. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Jean Delvare <khali@linux-fr.org>
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1 changed files with 20 additions and 6 deletions
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@ -61,6 +61,8 @@ struct s3c24xx_i2c {
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unsigned int msg_idx;
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unsigned int msg_ptr;
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unsigned int tx_setup;
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enum s3c24xx_i2c_state state;
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void __iomem *regs;
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@ -199,8 +201,11 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
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dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
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writeb(addr, i2c->regs + S3C2410_IICDS);
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// delay a bit and reset iiccon before setting start (per samsung)
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udelay(1);
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/* delay here to ensure the data byte has gotten onto the bus
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* before the transaction is started */
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ndelay(i2c->tx_setup);
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dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
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writel(iiccon, i2c->regs + S3C2410_IICCON);
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@ -322,7 +327,15 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
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if (!is_msgend(i2c)) {
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byte = i2c->msg->buf[i2c->msg_ptr++];
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writeb(byte, i2c->regs + S3C2410_IICDS);
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/* delay after writing the byte to allow the
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* data setup time on the bus, as writing the
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* data to the register causes the first bit
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* to appear on SDA, and SCL will change as
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* soon as the interrupt is acknowledged */
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ndelay(i2c->tx_setup);
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} else if (!is_lastmsg(i2c)) {
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/* we need to go to the next i2c message */
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@ -570,9 +583,10 @@ static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
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};
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static struct s3c24xx_i2c s3c24xx_i2c = {
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.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
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.wait = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
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.adap = {
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.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
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.wait = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
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.tx_setup = 50,
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.adap = {
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.name = "s3c2410-i2c",
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.owner = THIS_MODULE,
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.algo = &s3c24xx_i2c_algorithm,
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