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spi: s3c64xx: add support for google,gs101-spi
Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64 bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a Serror Interrupt is raised. Do the write reg accesses in 32 bits. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240207111516.2563218-5-tudor.ambarus@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
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1 changed files with 17 additions and 1 deletions
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@ -17,7 +17,7 @@
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#include <linux/platform_data/spi-s3c64xx.h>
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#include <linux/platform_data/spi-s3c64xx.h>
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#define MAX_SPI_PORTS 12
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#define MAX_SPI_PORTS 16
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#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
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#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
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#define AUTOSUSPEND_TIMEOUT 2000
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#define AUTOSUSPEND_TIMEOUT 2000
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@ -1534,6 +1534,19 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
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.quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
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.quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
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};
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};
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static const struct s3c64xx_spi_port_config gs101_spi_port_config = {
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.fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
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0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
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.rx_lvl_offset = 15,
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.tx_st_done = 25,
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.clk_div = 4,
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.high_speed = true,
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.clk_from_cmu = true,
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.has_loopback = true,
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.use_32bit_io = true,
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.quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
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};
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static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
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static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
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{
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{
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.name = "s3c2443-spi",
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.name = "s3c2443-spi",
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@ -1546,6 +1559,9 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
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};
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};
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static const struct of_device_id s3c64xx_spi_dt_match[] = {
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static const struct of_device_id s3c64xx_spi_dt_match[] = {
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{ .compatible = "google,gs101-spi",
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.data = &gs101_spi_port_config,
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},
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{ .compatible = "samsung,s3c2443-spi",
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{ .compatible = "samsung,s3c2443-spi",
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.data = (void *)&s3c2443_spi_port_config,
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.data = (void *)&s3c2443_spi_port_config,
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},
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},
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