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drm/amdgpu: fix bug set incorrect value to vce register
Set the proper bits for clockgating setup. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 1 additions and 1 deletions
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@ -175,7 +175,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
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WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
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WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
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data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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data &= ~0xffc00000;
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data &= ~0x3ff;
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
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data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
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data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
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