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ACPICA: Hardcode access width for the reset register.
The ACPI spec requires the reset register width to be 8, so we now hardcode it and ignore the FADT value. This provides/maintains compatibility with other ACPI implementations that have allowed BIOS code with bad register width values to go unnoticed. Matthew Garett, Bob Moore, Lv Zheng. Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lv Zheng <lv.zheng@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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2 changed files with 9 additions and 2 deletions
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@ -83,11 +83,17 @@ acpi_status acpi_reset(void)
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* For I/O space, write directly to the OSL. This bypasses the port
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* validation mechanism, which may block a valid write to the reset
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* register.
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* Spec section 4.7.3.6 requires register width to be 8.
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*
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* NOTE:
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* The ACPI spec requires the reset register width to be 8, so we
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* hardcode it here and ignore the FADT value. This maintains
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* compatibility with other ACPI implementations that have allowed
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* BIOS code with bad register width values to go unnoticed.
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*/
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status =
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acpi_os_write_port((acpi_io_address) reset_reg->address,
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acpi_gbl_FADT.reset_value, 8);
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acpi_gbl_FADT.reset_value,
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ACPI_RESET_REGISTER_WIDTH);
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} else {
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/* Write the reset value to the reset register */
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@ -349,6 +349,7 @@ typedef u32 acpi_physical_address;
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#define ACPI_PM1_REGISTER_WIDTH 16
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#define ACPI_PM2_REGISTER_WIDTH 8
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#define ACPI_PM_TIMER_WIDTH 32
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#define ACPI_RESET_REGISTER_WIDTH 8
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/* Names within the namespace are 4 bytes long */
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