reset: imx7: Add support for i.MX8MP SoC
i.MX8MP is a new SoC of i.MX8M family, it has same src IP inside but with different module layout, add support for it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Anson Huang
Philipp Zabel
parent
c4e181d6fe
commit
e08672c039
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@ -15,6 +15,7 @@
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#include <linux/regmap.h>
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#include <dt-bindings/reset/imx7-reset.h>
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#include <dt-bindings/reset/imx8mq-reset.h>
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#include <dt-bindings/reset/imx8mp-reset.h>
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struct imx7_src_signal {
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unsigned int offset, bit;
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@ -145,6 +146,18 @@ enum imx8mq_src_registers {
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SRC_DDRC2_RCR = 0x1004,
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};
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enum imx8mp_src_registers {
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SRC_SUPERMIX_RCR = 0x0018,
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SRC_AUDIOMIX_RCR = 0x001c,
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SRC_MLMIX_RCR = 0x0028,
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SRC_GPU2D_RCR = 0x0038,
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SRC_GPU3D_RCR = 0x003c,
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SRC_VPU_G1_RCR = 0x0048,
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SRC_VPU_G2_RCR = 0x004c,
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SRC_VPUVC8KE_RCR = 0x0050,
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SRC_NOC_RCR = 0x0054,
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};
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static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
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[IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
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[IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
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@ -253,6 +266,93 @@ static const struct imx7_src_variant variant_imx8mq = {
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},
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};
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static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
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[IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
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[IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
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[IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
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[IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
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[IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
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[IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
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[IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
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[IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
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[IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
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[IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
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[IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
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[IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
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[IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
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[IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
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[IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
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[IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
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[IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
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[IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
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[IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
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[IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
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[IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
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[IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
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[IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
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[IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
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[IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
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[IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
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[IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
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[IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
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[IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
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[IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
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[IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
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[IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
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[IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
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[IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
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[IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
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[IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
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[IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
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[IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) },
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};
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static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct imx7_src *imx7src = to_imx7_src(rcdev);
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const unsigned int bit = imx7src->signals[id].bit;
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unsigned int value = assert ? bit : 0;
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switch (id) {
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case IMX8MP_RESET_PCIEPHY:
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/*
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* wait for more than 10us to release phy g_rst and
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* btnrst
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*/
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if (!assert)
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udelay(10);
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break;
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case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
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value = assert ? 0 : bit;
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break;
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}
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return imx7_reset_update(imx7src, id, value);
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}
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static int imx8mp_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return imx8mp_reset_set(rcdev, id, true);
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}
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static int imx8mp_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return imx8mp_reset_set(rcdev, id, false);
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}
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static const struct imx7_src_variant variant_imx8mp = {
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.signals = imx8mp_src_signals,
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.signals_num = ARRAY_SIZE(imx8mp_src_signals),
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.ops = {
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.assert = imx8mp_reset_assert,
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.deassert = imx8mp_reset_deassert,
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},
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};
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static int imx7_reset_probe(struct platform_device *pdev)
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{
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struct imx7_src *imx7src;
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@ -283,6 +383,7 @@ static int imx7_reset_probe(struct platform_device *pdev)
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static const struct of_device_id imx7_reset_dt_ids[] = {
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{ .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
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{ .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
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{ .compatible = "fsl,imx8mp-src", .data = &variant_imx8mp },
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{ /* sentinel */ },
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};
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