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ASoC: atmel-classd: add the Audio Class D Amplifier
Add driver for the digital imput to PWM output stereo class D amplifier. It comes with filter, digitally controlled gain, an equalizer and a dmphase filter. Signed-off-by: Songjun Wu <songjun.wu@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
parent
6ff33f3902
commit
e0a25b6d18
4 changed files with 810 additions and 0 deletions
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@ -59,4 +59,13 @@ config SND_AT91_SOC_SAM9X5_WM8731
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help
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Say Y if you want to add support for audio SoC on an
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at91sam9x5 based board that is using WM8731 codec.
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config SND_ATMEL_SOC_CLASSD
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tristate "Atmel ASoC driver for boards using CLASSD"
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depends on ARCH_AT91 || COMPILE_TEST
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select SND_ATMEL_SOC_DMA
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select REGMAP_MMIO
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help
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Say Y if you want to add support for Atmel ASoC driver for boards using
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CLASSD.
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endif
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@ -11,7 +11,9 @@ obj-$(CONFIG_SND_ATMEL_SOC_SSC) += snd-soc-atmel_ssc_dai.o
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snd-soc-sam9g20-wm8731-objs := sam9g20_wm8731.o
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snd-atmel-soc-wm8904-objs := atmel_wm8904.o
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snd-soc-sam9x5-wm8731-objs := sam9x5_wm8731.o
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snd-atmel-soc-classd-objs := atmel-classd.o
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obj-$(CONFIG_SND_AT91_SOC_SAM9G20_WM8731) += snd-soc-sam9g20-wm8731.o
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obj-$(CONFIG_SND_ATMEL_SOC_WM8904) += snd-atmel-soc-wm8904.o
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obj-$(CONFIG_SND_AT91_SOC_SAM9X5_WM8731) += snd-soc-sam9x5-wm8731.o
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obj-$(CONFIG_SND_ATMEL_SOC_CLASSD) += snd-atmel-soc-classd.o
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679
sound/soc/atmel/atmel-classd.c
Normal file
679
sound/soc/atmel/atmel-classd.c
Normal file
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@ -0,0 +1,679 @@
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/* Atmel ALSA SoC Audio Class D Amplifier (CLASSD) driver
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*
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* Copyright (C) 2015 Atmel
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*
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* Author: Songjun Wu <songjun.wu@atmel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or later
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* as published by the Free Software Foundation.
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*/
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#include <linux/of.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/tlv.h>
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#include "atmel-classd.h"
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struct atmel_classd_pdata {
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bool non_overlap_enable;
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int non_overlap_time;
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int pwm_type;
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const char *card_name;
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};
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struct atmel_classd {
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dma_addr_t phy_base;
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struct regmap *regmap;
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struct clk *pclk;
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struct clk *gclk;
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struct clk *aclk;
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int irq;
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const struct atmel_classd_pdata *pdata;
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};
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#ifdef CONFIG_OF
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static const struct of_device_id atmel_classd_of_match[] = {
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{
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.compatible = "atmel,sama5d2-classd",
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}, {
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/* sentinel */
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}
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};
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MODULE_DEVICE_TABLE(of, atmel_classd_of_match);
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static struct atmel_classd_pdata *atmel_classd_dt_init(struct device *dev)
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{
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struct device_node *np = dev->of_node;
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struct atmel_classd_pdata *pdata;
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const char *pwm_type;
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int ret;
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if (!np) {
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dev_err(dev, "device node not found\n");
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return ERR_PTR(-EINVAL);
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}
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pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return ERR_PTR(-ENOMEM);
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ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type);
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if ((ret == 0) && (strcmp(pwm_type, "diff") == 0))
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pdata->pwm_type = CLASSD_MR_PWMTYP_DIFF;
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else
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pdata->pwm_type = CLASSD_MR_PWMTYP_SINGLE;
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ret = of_property_read_u32(np,
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"atmel,non-overlap-time", &pdata->non_overlap_time);
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if (ret)
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pdata->non_overlap_enable = false;
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else
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pdata->non_overlap_enable = true;
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ret = of_property_read_string(np, "atmel,model", &pdata->card_name);
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if (ret)
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pdata->card_name = "CLASSD";
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return pdata;
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}
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#else
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static inline struct atmel_classd_pdata *
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atmel_classd_dt_init(struct device *dev)
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{
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return ERR_PTR(-EINVAL);
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}
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#endif
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#define ATMEL_CLASSD_RATES (SNDRV_PCM_RATE_8000 \
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| SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 \
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| SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 \
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| SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 \
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| SNDRV_PCM_RATE_96000)
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static const struct snd_pcm_hardware atmel_classd_hw = {
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.info = SNDRV_PCM_INFO_MMAP
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| SNDRV_PCM_INFO_MMAP_VALID
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| SNDRV_PCM_INFO_INTERLEAVED
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| SNDRV_PCM_INFO_RESUME
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| SNDRV_PCM_INFO_PAUSE,
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.formats = (SNDRV_PCM_FMTBIT_S16_LE),
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.rates = ATMEL_CLASSD_RATES,
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.rate_min = 8000,
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.rate_max = 96000,
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.channels_min = 2,
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.channels_max = 2,
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.buffer_bytes_max = 64 * 1024,
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.period_bytes_min = 256,
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.period_bytes_max = 32 * 1024,
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.periods_min = 2,
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.periods_max = 256,
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};
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#define ATMEL_CLASSD_PREALLOC_BUF_SIZE (64 * 1024)
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/* cpu dai component */
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static int atmel_classd_cpu_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
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regmap_write(dd->regmap, CLASSD_THR, 0x0);
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return clk_prepare_enable(dd->pclk);
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}
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static void atmel_classd_cpu_dai_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
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clk_disable_unprepare(dd->pclk);
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}
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static const struct snd_soc_dai_ops atmel_classd_cpu_dai_ops = {
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.startup = atmel_classd_cpu_dai_startup,
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.shutdown = atmel_classd_cpu_dai_shutdown,
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};
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static struct snd_soc_dai_driver atmel_classd_cpu_dai = {
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.playback = {
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.channels_min = 2,
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.channels_max = 2,
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.rates = ATMEL_CLASSD_RATES,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,},
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.ops = &atmel_classd_cpu_dai_ops,
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};
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static const struct snd_soc_component_driver atmel_classd_cpu_dai_component = {
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.name = "atmel-classd",
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};
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/* platform */
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static int
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atmel_classd_platform_configure_dma(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct dma_slave_config *slave_config)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
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if (params_physical_width(params) != 16) {
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dev_err(rtd->platform->dev,
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"only supports 16-bit audio data\n");
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return -EINVAL;
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}
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slave_config->direction = DMA_MEM_TO_DEV;
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slave_config->dst_addr = dd->phy_base + CLASSD_THR;
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slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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slave_config->dst_maxburst = 1;
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slave_config->src_maxburst = 1;
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slave_config->device_fc = false;
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return 0;
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}
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static const struct snd_dmaengine_pcm_config
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atmel_classd_dmaengine_pcm_config = {
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.prepare_slave_config = atmel_classd_platform_configure_dma,
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.pcm_hardware = &atmel_classd_hw,
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.prealloc_buffer_size = ATMEL_CLASSD_PREALLOC_BUF_SIZE,
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};
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/* codec */
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static const char * const mono_mode_text[] = {
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"mix", "sat", "left", "right"
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};
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static SOC_ENUM_SINGLE_DECL(classd_mono_mode_enum,
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CLASSD_INTPMR, CLASSD_INTPMR_MONO_MODE_SHIFT,
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mono_mode_text);
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static const char * const eqcfg_text[] = {
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"Treble-12dB", "Treble-6dB",
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"Medium-8dB", "Medium-3dB",
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"Bass-12dB", "Bass-6dB",
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"0 dB",
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"Bass+6dB", "Bass+12dB",
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"Medium+3dB", "Medium+8dB",
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"Treble+6dB", "Treble+12dB",
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};
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static const unsigned int eqcfg_value[] = {
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CLASSD_INTPMR_EQCFG_T_CUT_12, CLASSD_INTPMR_EQCFG_T_CUT_6,
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CLASSD_INTPMR_EQCFG_M_CUT_8, CLASSD_INTPMR_EQCFG_M_CUT_3,
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CLASSD_INTPMR_EQCFG_B_CUT_12, CLASSD_INTPMR_EQCFG_B_CUT_6,
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CLASSD_INTPMR_EQCFG_FLAT,
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CLASSD_INTPMR_EQCFG_B_BOOST_6, CLASSD_INTPMR_EQCFG_B_BOOST_12,
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CLASSD_INTPMR_EQCFG_M_BOOST_3, CLASSD_INTPMR_EQCFG_M_BOOST_8,
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CLASSD_INTPMR_EQCFG_T_BOOST_6, CLASSD_INTPMR_EQCFG_T_BOOST_12,
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};
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static SOC_VALUE_ENUM_SINGLE_DECL(classd_eqcfg_enum,
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CLASSD_INTPMR, CLASSD_INTPMR_EQCFG_SHIFT, 0xf,
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eqcfg_text, eqcfg_value);
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static const DECLARE_TLV_DB_SCALE(classd_digital_tlv, -7800, 100, 1);
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static const struct snd_kcontrol_new atmel_classd_snd_controls[] = {
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SOC_DOUBLE_TLV("Playback Volume", CLASSD_INTPMR,
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CLASSD_INTPMR_ATTL_SHIFT, CLASSD_INTPMR_ATTR_SHIFT,
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78, 1, classd_digital_tlv),
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SOC_SINGLE("Deemphasis Switch", CLASSD_INTPMR,
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CLASSD_INTPMR_DEEMP_SHIFT, 1, 0),
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SOC_SINGLE("Mono Switch", CLASSD_INTPMR, CLASSD_INTPMR_MONO_SHIFT, 1, 0),
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SOC_SINGLE("Swap Switch", CLASSD_INTPMR, CLASSD_INTPMR_SWAP_SHIFT, 1, 0),
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SOC_ENUM("Mono Mode", classd_mono_mode_enum),
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SOC_ENUM("EQ", classd_eqcfg_enum),
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};
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static const char * const pwm_type[] = {
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"Single ended", "Differential"
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};
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static int atmel_classd_codec_probe(struct snd_soc_codec *codec)
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{
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struct snd_soc_card *card = snd_soc_codec_get_drvdata(codec);
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struct atmel_classd *dd = snd_soc_card_get_drvdata(card);
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const struct atmel_classd_pdata *pdata = dd->pdata;
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u32 mask, val;
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mask = CLASSD_MR_PWMTYP_MASK;
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val = pdata->pwm_type << CLASSD_MR_PWMTYP_SHIFT;
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mask |= CLASSD_MR_NON_OVERLAP_MASK;
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if (pdata->non_overlap_enable) {
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val |= (CLASSD_MR_NON_OVERLAP_EN
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<< CLASSD_MR_NON_OVERLAP_SHIFT);
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mask |= CLASSD_MR_NOVR_VAL_MASK;
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switch (pdata->non_overlap_time) {
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case 5:
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val |= (CLASSD_MR_NOVR_VAL_5NS
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<< CLASSD_MR_NOVR_VAL_SHIFT);
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break;
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case 10:
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val |= (CLASSD_MR_NOVR_VAL_10NS
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<< CLASSD_MR_NOVR_VAL_SHIFT);
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break;
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case 15:
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val |= (CLASSD_MR_NOVR_VAL_15NS
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<< CLASSD_MR_NOVR_VAL_SHIFT);
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break;
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case 20:
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val |= (CLASSD_MR_NOVR_VAL_20NS
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<< CLASSD_MR_NOVR_VAL_SHIFT);
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break;
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default:
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val |= (CLASSD_MR_NOVR_VAL_10NS
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<< CLASSD_MR_NOVR_VAL_SHIFT);
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dev_warn(codec->dev,
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"non-overlapping value %d is invalid, the default value 10 is specified\n",
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pdata->non_overlap_time);
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break;
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}
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}
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snd_soc_update_bits(codec, CLASSD_MR, mask, val);
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dev_info(codec->dev,
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"PWM modulation type is %s, non-overlapping is %s\n",
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pwm_type[pdata->pwm_type],
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pdata->non_overlap_enable?"enabled":"disabled");
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return 0;
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}
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static struct regmap *atmel_classd_codec_get_remap(struct device *dev)
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{
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return dev_get_regmap(dev, NULL);
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}
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static struct snd_soc_codec_driver soc_codec_dev_classd = {
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.probe = atmel_classd_codec_probe,
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.controls = atmel_classd_snd_controls,
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.num_controls = ARRAY_SIZE(atmel_classd_snd_controls),
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.get_regmap = atmel_classd_codec_get_remap,
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};
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/* codec dai component */
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static int atmel_classd_codec_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *codec_dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
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int ret;
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ret = clk_prepare_enable(dd->aclk);
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if (ret)
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return ret;
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return clk_prepare_enable(dd->gclk);
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}
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static int atmel_classd_codec_dai_digital_mute(struct snd_soc_dai *codec_dai,
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int mute)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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u32 mask, val;
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mask = CLASSD_MR_LMUTE_MASK | CLASSD_MR_RMUTE_MASK;
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if (mute)
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val = mask;
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else
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val = 0;
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snd_soc_update_bits(codec, CLASSD_MR, mask, val);
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return 0;
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}
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#define CLASSD_ACLK_RATE_11M2896_MPY_8 (112896 * 100 * 8)
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#define CLASSD_ACLK_RATE_12M288_MPY_8 (12228 * 1000 * 8)
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static struct {
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int rate;
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int sample_rate;
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int dsp_clk;
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unsigned long aclk_rate;
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} const sample_rates[] = {
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{ 8000, CLASSD_INTPMR_FRAME_8K,
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CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_ACLK_RATE_12M288_MPY_8 },
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{ 16000, CLASSD_INTPMR_FRAME_16K,
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CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_ACLK_RATE_12M288_MPY_8 },
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{ 32000, CLASSD_INTPMR_FRAME_32K,
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CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_ACLK_RATE_12M288_MPY_8 },
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{ 48000, CLASSD_INTPMR_FRAME_48K,
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CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_ACLK_RATE_12M288_MPY_8 },
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{ 96000, CLASSD_INTPMR_FRAME_96K,
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CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_ACLK_RATE_12M288_MPY_8 },
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{ 22050, CLASSD_INTPMR_FRAME_22K,
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CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_ACLK_RATE_11M2896_MPY_8 },
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{ 44100, CLASSD_INTPMR_FRAME_44K,
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CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_ACLK_RATE_11M2896_MPY_8 },
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{ 88200, CLASSD_INTPMR_FRAME_88K,
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CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_ACLK_RATE_11M2896_MPY_8 },
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};
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static int
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atmel_classd_codec_dai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *codec_dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
|
||||
struct snd_soc_codec *codec = codec_dai->codec;
|
||||
int fs;
|
||||
int i, best, best_val, cur_val, ret;
|
||||
u32 mask, val;
|
||||
|
||||
fs = params_rate(params);
|
||||
|
||||
best = 0;
|
||||
best_val = abs(fs - sample_rates[0].rate);
|
||||
for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
|
||||
/* Closest match */
|
||||
cur_val = abs(fs - sample_rates[i].rate);
|
||||
if (cur_val < best_val) {
|
||||
best = i;
|
||||
best_val = cur_val;
|
||||
}
|
||||
}
|
||||
|
||||
dev_dbg(codec->dev,
|
||||
"Selected SAMPLE_RATE of %dHz, ACLK_RATE of %ldHz\n",
|
||||
sample_rates[best].rate, sample_rates[best].aclk_rate);
|
||||
|
||||
clk_disable_unprepare(dd->gclk);
|
||||
clk_disable_unprepare(dd->aclk);
|
||||
|
||||
ret = clk_set_rate(dd->aclk, sample_rates[best].aclk_rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mask = CLASSD_INTPMR_DSP_CLK_FREQ_MASK | CLASSD_INTPMR_FRAME_MASK;
|
||||
val = (sample_rates[best].dsp_clk << CLASSD_INTPMR_DSP_CLK_FREQ_SHIFT)
|
||||
| (sample_rates[best].sample_rate << CLASSD_INTPMR_FRAME_SHIFT);
|
||||
|
||||
snd_soc_update_bits(codec, CLASSD_INTPMR, mask, val);
|
||||
|
||||
ret = clk_prepare_enable(dd->aclk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return clk_prepare_enable(dd->gclk);
|
||||
}
|
||||
|
||||
static void
|
||||
atmel_classd_codec_dai_shutdown(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *codec_dai)
|
||||
{
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
|
||||
|
||||
clk_disable_unprepare(dd->gclk);
|
||||
clk_disable_unprepare(dd->aclk);
|
||||
}
|
||||
|
||||
static int atmel_classd_codec_dai_prepare(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *codec_dai)
|
||||
{
|
||||
struct snd_soc_codec *codec = codec_dai->codec;
|
||||
|
||||
snd_soc_update_bits(codec, CLASSD_MR,
|
||||
CLASSD_MR_LEN_MASK | CLASSD_MR_REN_MASK,
|
||||
(CLASSD_MR_LEN_DIS << CLASSD_MR_LEN_SHIFT)
|
||||
|(CLASSD_MR_REN_DIS << CLASSD_MR_REN_SHIFT));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int atmel_classd_codec_dai_trigger(struct snd_pcm_substream *substream,
|
||||
int cmd, struct snd_soc_dai *codec_dai)
|
||||
{
|
||||
struct snd_soc_codec *codec = codec_dai->codec;
|
||||
u32 mask, val;
|
||||
|
||||
mask = CLASSD_MR_LEN_MASK | CLASSD_MR_REN_MASK;
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
val = mask;
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
val = (CLASSD_MR_LEN_DIS << CLASSD_MR_LEN_SHIFT)
|
||||
| (CLASSD_MR_REN_DIS << CLASSD_MR_REN_SHIFT);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
snd_soc_update_bits(codec, CLASSD_MR, mask, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops atmel_classd_codec_dai_ops = {
|
||||
.digital_mute = atmel_classd_codec_dai_digital_mute,
|
||||
.startup = atmel_classd_codec_dai_startup,
|
||||
.shutdown = atmel_classd_codec_dai_shutdown,
|
||||
.hw_params = atmel_classd_codec_dai_hw_params,
|
||||
.prepare = atmel_classd_codec_dai_prepare,
|
||||
.trigger = atmel_classd_codec_dai_trigger,
|
||||
};
|
||||
|
||||
#define ATMEL_CLASSD_CODEC_DAI_NAME "atmel-classd-hifi"
|
||||
|
||||
static struct snd_soc_dai_driver atmel_classd_codec_dai = {
|
||||
.name = ATMEL_CLASSD_CODEC_DAI_NAME,
|
||||
.playback = {
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rates = ATMEL_CLASSD_RATES,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
.ops = &atmel_classd_codec_dai_ops,
|
||||
};
|
||||
|
||||
/* ASoC sound card */
|
||||
static int atmel_classd_asoc_card_init(struct device *dev,
|
||||
struct snd_soc_card *card)
|
||||
{
|
||||
struct snd_soc_dai_link *dai_link;
|
||||
struct atmel_classd *dd = snd_soc_card_get_drvdata(card);
|
||||
|
||||
dai_link = devm_kzalloc(dev, sizeof(*dai_link), GFP_KERNEL);
|
||||
if (!dai_link)
|
||||
return -ENOMEM;
|
||||
|
||||
dai_link->name = "CLASSD";
|
||||
dai_link->stream_name = "CLASSD PCM";
|
||||
dai_link->codec_dai_name = ATMEL_CLASSD_CODEC_DAI_NAME;
|
||||
dai_link->cpu_dai_name = dev_name(dev);
|
||||
dai_link->codec_name = dev_name(dev);
|
||||
dai_link->platform_name = dev_name(dev);
|
||||
|
||||
card->dai_link = dai_link;
|
||||
card->num_links = 1;
|
||||
card->name = dd->pdata->card_name;
|
||||
card->dev = dev;
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
/* regmap configuration */
|
||||
static const struct reg_default atmel_classd_reg_defaults[] = {
|
||||
{ CLASSD_INTPMR, 0x00301212 },
|
||||
};
|
||||
|
||||
#define ATMEL_CLASSD_REG_MAX 0xE4
|
||||
static const struct regmap_config atmel_classd_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = ATMEL_CLASSD_REG_MAX,
|
||||
|
||||
.cache_type = REGCACHE_FLAT,
|
||||
.reg_defaults = atmel_classd_reg_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(atmel_classd_reg_defaults),
|
||||
};
|
||||
|
||||
static int atmel_classd_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct atmel_classd *dd;
|
||||
struct resource *res;
|
||||
void __iomem *io_base;
|
||||
const struct atmel_classd_pdata *pdata;
|
||||
struct snd_soc_card *card;
|
||||
int ret;
|
||||
|
||||
pdata = dev_get_platdata(dev);
|
||||
if (!pdata) {
|
||||
pdata = atmel_classd_dt_init(dev);
|
||||
if (IS_ERR(pdata))
|
||||
return PTR_ERR(pdata);
|
||||
}
|
||||
|
||||
dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
|
||||
if (!dd)
|
||||
return -ENOMEM;
|
||||
|
||||
dd->pdata = pdata;
|
||||
|
||||
dd->irq = platform_get_irq(pdev, 0);
|
||||
if (dd->irq < 0) {
|
||||
ret = dd->irq;
|
||||
dev_err(dev, "failed to could not get irq: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dd->pclk = devm_clk_get(dev, "pclk");
|
||||
if (IS_ERR(dd->pclk)) {
|
||||
ret = PTR_ERR(dd->pclk);
|
||||
dev_err(dev, "failed to get peripheral clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dd->gclk = devm_clk_get(dev, "gclk");
|
||||
if (IS_ERR(dd->gclk)) {
|
||||
ret = PTR_ERR(dd->gclk);
|
||||
dev_err(dev, "failed to get GCK clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dd->aclk = devm_clk_get(dev, "aclk");
|
||||
if (IS_ERR(dd->aclk)) {
|
||||
ret = PTR_ERR(dd->aclk);
|
||||
dev_err(dev, "failed to get audio clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(dev, "no memory resource\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
io_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(io_base)) {
|
||||
ret = PTR_ERR(io_base);
|
||||
dev_err(dev, "failed to remap register memory: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dd->phy_base = res->start;
|
||||
|
||||
dd->regmap = devm_regmap_init_mmio(dev, io_base,
|
||||
&atmel_classd_regmap_config);
|
||||
if (IS_ERR(dd->regmap)) {
|
||||
ret = PTR_ERR(dd->regmap);
|
||||
dev_err(dev, "failed to init register map: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_snd_soc_register_component(dev,
|
||||
&atmel_classd_cpu_dai_component,
|
||||
&atmel_classd_cpu_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(dev, "could not register CPU DAI: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_snd_dmaengine_pcm_register(dev,
|
||||
&atmel_classd_dmaengine_pcm_config,
|
||||
0);
|
||||
if (ret) {
|
||||
dev_err(dev, "could not register platform: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = snd_soc_register_codec(dev, &soc_codec_dev_classd,
|
||||
&atmel_classd_codec_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(dev, "could not register codec: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* register sound card */
|
||||
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
|
||||
if (!card)
|
||||
return -ENOMEM;
|
||||
|
||||
snd_soc_card_set_drvdata(card, dd);
|
||||
platform_set_drvdata(pdev, card);
|
||||
|
||||
ret = atmel_classd_asoc_card_init(dev, card);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to init sound card\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_snd_soc_register_card(dev, card);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register sound card: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int atmel_classd_remove(struct platform_device *pdev)
|
||||
{
|
||||
snd_soc_unregister_codec(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver atmel_classd_driver = {
|
||||
.driver = {
|
||||
.name = "atmel-classd",
|
||||
.of_match_table = of_match_ptr(atmel_classd_of_match),
|
||||
.pm = &snd_soc_pm_ops,
|
||||
},
|
||||
.probe = atmel_classd_probe,
|
||||
.remove = atmel_classd_remove,
|
||||
};
|
||||
module_platform_driver(atmel_classd_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Atmel ClassD driver under ALSA SoC architecture");
|
||||
MODULE_AUTHOR("Songjun Wu <songjun.wu@atmel.com>");
|
||||
MODULE_LICENSE("GPL");
|
120
sound/soc/atmel/atmel-classd.h
Normal file
120
sound/soc/atmel/atmel-classd.h
Normal file
|
@ -0,0 +1,120 @@
|
|||
#ifndef __ATMEL_CLASSD_H_
|
||||
#define __ATMEL_CLASSD_H_
|
||||
|
||||
#define CLASSD_CR 0x00000000
|
||||
#define CLASSD_CR_RESET 0x1
|
||||
|
||||
#define CLASSD_MR 0x00000004
|
||||
|
||||
#define CLASSD_MR_LEN_DIS 0x0
|
||||
#define CLASSD_MR_LEN_EN 0x1
|
||||
#define CLASSD_MR_LEN_MASK (0x1 << 0)
|
||||
#define CLASSD_MR_LEN_SHIFT (0)
|
||||
|
||||
#define CLASSD_MR_LMUTE_DIS 0x0
|
||||
#define CLASSD_MR_LMUTE_EN 0x1
|
||||
#define CLASSD_MR_LMUTE_SHIFT (0x1)
|
||||
#define CLASSD_MR_LMUTE_MASK (0x1 << 1)
|
||||
|
||||
#define CLASSD_MR_REN_DIS 0x0
|
||||
#define CLASSD_MR_REN_EN 0x1
|
||||
#define CLASSD_MR_REN_MASK (0x1 << 4)
|
||||
#define CLASSD_MR_REN_SHIFT (4)
|
||||
|
||||
#define CLASSD_MR_RMUTE_DIS 0x0
|
||||
#define CLASSD_MR_RMUTE_EN 0x1
|
||||
#define CLASSD_MR_RMUTE_SHIFT (0x5)
|
||||
#define CLASSD_MR_RMUTE_MASK (0x1 << 5)
|
||||
|
||||
#define CLASSD_MR_PWMTYP_SINGLE 0x0
|
||||
#define CLASSD_MR_PWMTYP_DIFF 0x1
|
||||
#define CLASSD_MR_PWMTYP_MASK (0x1 << 8)
|
||||
#define CLASSD_MR_PWMTYP_SHIFT (8)
|
||||
|
||||
#define CLASSD_MR_NON_OVERLAP_DIS 0x0
|
||||
#define CLASSD_MR_NON_OVERLAP_EN 0x1
|
||||
#define CLASSD_MR_NON_OVERLAP_MASK (0x1 << 16)
|
||||
#define CLASSD_MR_NON_OVERLAP_SHIFT (16)
|
||||
|
||||
#define CLASSD_MR_NOVR_VAL_5NS 0x0
|
||||
#define CLASSD_MR_NOVR_VAL_10NS 0x1
|
||||
#define CLASSD_MR_NOVR_VAL_15NS 0x2
|
||||
#define CLASSD_MR_NOVR_VAL_20NS 0x3
|
||||
#define CLASSD_MR_NOVR_VAL_MASK (0x3 << 20)
|
||||
#define CLASSD_MR_NOVR_VAL_SHIFT (20)
|
||||
|
||||
#define CLASSD_INTPMR 0x00000008
|
||||
|
||||
#define CLASSD_INTPMR_ATTL_MASK (0x3f << 0)
|
||||
#define CLASSD_INTPMR_ATTL_SHIFT (0)
|
||||
#define CLASSD_INTPMR_ATTR_MASK (0x3f << 8)
|
||||
#define CLASSD_INTPMR_ATTR_SHIFT (8)
|
||||
|
||||
#define CLASSD_INTPMR_DSP_CLK_FREQ_12M288 0x0
|
||||
#define CLASSD_INTPMR_DSP_CLK_FREQ_11M2896 0x1
|
||||
#define CLASSD_INTPMR_DSP_CLK_FREQ_MASK (0x1 << 16)
|
||||
#define CLASSD_INTPMR_DSP_CLK_FREQ_SHIFT (16)
|
||||
|
||||
#define CLASSD_INTPMR_DEEMP_DIS 0x0
|
||||
#define CLASSD_INTPMR_DEEMP_EN 0x1
|
||||
#define CLASSD_INTPMR_DEEMP_MASK (0x1 << 18)
|
||||
#define CLASSD_INTPMR_DEEMP_SHIFT (18)
|
||||
|
||||
#define CLASSD_INTPMR_SWAP_LEFT_ON_LSB 0x0
|
||||
#define CLASSD_INTPMR_SWAP_RIGHT_ON_LSB 0x1
|
||||
#define CLASSD_INTPMR_SWAP_MASK (0x1 << 19)
|
||||
#define CLASSD_INTPMR_SWAP_SHIFT (19)
|
||||
|
||||
#define CLASSD_INTPMR_FRAME_8K 0x0
|
||||
#define CLASSD_INTPMR_FRAME_16K 0x1
|
||||
#define CLASSD_INTPMR_FRAME_32K 0x2
|
||||
#define CLASSD_INTPMR_FRAME_48K 0x3
|
||||
#define CLASSD_INTPMR_FRAME_96K 0x4
|
||||
#define CLASSD_INTPMR_FRAME_22K 0x5
|
||||
#define CLASSD_INTPMR_FRAME_44K 0x6
|
||||
#define CLASSD_INTPMR_FRAME_88K 0x7
|
||||
#define CLASSD_INTPMR_FRAME_MASK (0x7 << 20)
|
||||
#define CLASSD_INTPMR_FRAME_SHIFT (20)
|
||||
|
||||
#define CLASSD_INTPMR_EQCFG_FLAT 0x0
|
||||
#define CLASSD_INTPMR_EQCFG_B_BOOST_12 0x1
|
||||
#define CLASSD_INTPMR_EQCFG_B_BOOST_6 0x2
|
||||
#define CLASSD_INTPMR_EQCFG_B_CUT_12 0x3
|
||||
#define CLASSD_INTPMR_EQCFG_B_CUT_6 0x4
|
||||
#define CLASSD_INTPMR_EQCFG_M_BOOST_3 0x5
|
||||
#define CLASSD_INTPMR_EQCFG_M_BOOST_8 0x6
|
||||
#define CLASSD_INTPMR_EQCFG_M_CUT_3 0x7
|
||||
#define CLASSD_INTPMR_EQCFG_M_CUT_8 0x8
|
||||
#define CLASSD_INTPMR_EQCFG_T_BOOST_12 0x9
|
||||
#define CLASSD_INTPMR_EQCFG_T_BOOST_6 0xa
|
||||
#define CLASSD_INTPMR_EQCFG_T_CUT_12 0xb
|
||||
#define CLASSD_INTPMR_EQCFG_T_CUT_6 0xc
|
||||
#define CLASSD_INTPMR_EQCFG_SHIFT (24)
|
||||
|
||||
#define CLASSD_INTPMR_MONO_DIS 0x0
|
||||
#define CLASSD_INTPMR_MONO_EN 0x1
|
||||
#define CLASSD_INTPMR_MONO_MASK (0x1 << 28)
|
||||
#define CLASSD_INTPMR_MONO_SHIFT (28)
|
||||
|
||||
#define CLASSD_INTPMR_MONO_MODE_MIX 0x0
|
||||
#define CLASSD_INTPMR_MONO_MODE_SAT 0x1
|
||||
#define CLASSD_INTPMR_MONO_MODE_LEFT 0x2
|
||||
#define CLASSD_INTPMR_MONO_MODE_RIGHT 0x3
|
||||
#define CLASSD_INTPMR_MONO_MODE_MASK (0x3 << 29)
|
||||
#define CLASSD_INTPMR_MONO_MODE_SHIFT (29)
|
||||
|
||||
#define CLASSD_INTSR 0x0000000c
|
||||
|
||||
#define CLASSD_THR 0x00000010
|
||||
|
||||
#define CLASSD_IER 0x00000014
|
||||
|
||||
#define CLASSD_IDR 0x00000018
|
||||
|
||||
#define CLASSD_IMR 0x0000001c
|
||||
|
||||
#define CLASSD_ISR 0x00000020
|
||||
|
||||
#define CLASSD_WPMR 0x000000e4
|
||||
|
||||
#endif
|
Loading…
Reference in a new issue