Renesas ARM Based SoC R8a7740 CCF and Timers Updates for v3.18
When booting using the r8a7740/armadillo800eva using dt-reference: * Use CCF to initialise clocks via DT * Initialise timers via DT -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJT/BT6AAoJENfPZGlqN0++MPwQAIzGfi79jMY14Xep790KD17A wvae1QGyLpIPH/nyVr6iEbHiX3YBfW4kcvrQ1GWOG19tFoWlc4fiOK1ZcCAnydFD SU1lnkpT6+ZIEeFkdXwMyux2lVeaZSQHOInT7UYZnWLUhfkCkuf7IJNvrYNMGb+Z 3viXbRkqz1cz9nyIRDmryq0IZO8d7ZNFhOSdTTq3Rjzn32V68I2HZVGKOu00bI7J UEpEXlPqAs8R90NkyLvoEaN3d0NHz6TrX8VqgWW6cNxu8Kv3OCLhkjmGdjmWXZ3P SuVXJv37vcjkKXuclRVaPV8GcQgJZO34RSUpc0HMYJyutEp3ANLxujT7zFSwJEvK vUZkPGpzWY9+icqfPOoGlEoGIcVGTnB1rH25ap5y/b7SnfNsw2dJyhx/Mr8nln2b SwTMXxZZvP8V2qK7CrXU5TXnhl2nYJwvjU8ORhe3ZJrAOmrlfrBNFBTzm/8Txik7 /JUFjInTkOoLX4a0vjJlwc/rRAAe8jASmpWTC6N9mTzJhY7gySpXwxWOwT2f/+YR otDz1JS4EpqRFiK3ptnPVJ7sVpamz5glCLCCZWMZdwWG7G1B+daXD2shTPk7aup5 EsN0YKIjMfdTL5sQcQIhS5Yoj/KJEhwkNny+EsMofExKZeQerqQT3SG9a798xxLR 8ACepiF2VECSLNCWvUKj =uu7K -----END PGP SIGNATURE----- Merge tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Renesas ARM Based SoC R8a7740 CCF and Timers Updates for v3.18" from Simon Horman: When booting using the r8a7740/armadillo800eva using dt-reference: * Use CCF to initialise clocks via DT * Initialise timers via DT Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7740: Remove r8a7740_add_standard_devices_dt ARM: shmobile: armadillo800eva-reference: Do not use r8a7740_add_standard_devices_dt() ARM: shmobile: armadillo800eva-reference: Enable CMT1 in device tree ARM: shmobile: r8a7740: Add CMT1 device to DT ARM: shmobile: armadillo800eva-reference: add clock overrides to DTS ARM: shmobile: r8a7740: add MSTP clock assignments to DT ARM: shmobile: r8a7740: add SoC clocks to DTS ARM: shmobile: r8a7740: clock register bits
This commit is contained in:
Arnd Bergmann
commit
e0ace5fc33
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@ -178,6 +178,23 @@
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};
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};
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&extal1_clk {
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clock-frequency = <25000000>;
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};
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&extal2_clk {
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clock-frequency = <48000000>;
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};
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&fsibck_clk {
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clock-frequency = <12288000>;
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};
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&cpg_clocks {
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renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */
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};
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&cmt1 {
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status = "ok";
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};
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&i2c0 {
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status = "okay";
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touchscreen@55 {
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@ -10,6 +10,7 @@
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/r8a7740-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@ -40,6 +41,18 @@
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmt1: timer@e6138000 {
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compatible = "renesas,cmt-48";
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reg = <0xe6138000 0x170>;
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interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
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clock-names = "fck";
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renesas,channels-mask = <0x3f>;
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status = "disabled";
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};
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/* irqpin0: IRQ0 - IRQ7 */
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irqpin0: irqpin@e6900000 {
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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@ -125,7 +138,7 @@
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reg = <0xe9a00000 0x800>,
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<0xe9a01800 0x800>;
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interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
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/* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */
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clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
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phy-mode = "mii";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -141,6 +154,7 @@
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0 202 IRQ_TYPE_LEVEL_HIGH
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0 203 IRQ_TYPE_LEVEL_HIGH
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0 204 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
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status = "disabled";
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};
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@ -153,6 +167,7 @@
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0 71 IRQ_TYPE_LEVEL_HIGH
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0 72 IRQ_TYPE_LEVEL_HIGH
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0 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
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status = "disabled";
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};
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@ -160,6 +175,8 @@
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c40000 0x100>;
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interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -167,6 +184,8 @@
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c50000 0x100>;
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interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -174,6 +193,8 @@
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c60000 0x100>;
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interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -181,6 +202,8 @@
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c70000 0x100>;
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interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -188,6 +211,8 @@
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c80000 0x100>;
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -195,6 +220,8 @@
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6cb0000 0x100>;
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -202,6 +229,8 @@
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6cc0000 0x100>;
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -209,6 +238,8 @@
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6cd0000 0x100>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -216,6 +247,8 @@
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compatible = "renesas,scifb-r8a7740", "renesas,scifb";
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reg = <0xe6c30000 0x100>;
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -239,6 +272,7 @@
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tpu: pwm@e6600000 {
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compatible = "renesas,tpu-r8a7740", "renesas,tpu";
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reg = <0xe6600000 0x100>;
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clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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@ -248,6 +282,7 @@
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reg = <0xe6bd0000 0x100>;
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interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
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0 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_MMC>;
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status = "disabled";
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};
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@ -257,6 +292,7 @@
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interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
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0 118 IRQ_TYPE_LEVEL_HIGH
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0 119 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@ -268,6 +304,7 @@
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interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
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0 122 IRQ_TYPE_LEVEL_HIGH
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0 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@ -279,6 +316,7 @@
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interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
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0 126 IRQ_TYPE_LEVEL_HIGH
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0 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@ -289,6 +327,186 @@
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compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
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reg = <0xfe1f0000 0x400>;
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interrupts = <0 9 0x4>;
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clocks = <&mstp3_clks R8A7740_CLK_FSI>;
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status = "disabled";
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* External root clock */
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extalr_clk: extalr_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "extalr";
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};
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extal1_clk: extal1_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "extal1";
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};
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extal2_clk: extal2_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "extal2";
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};
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dv_clk: dv_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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clock-output-names = "dv";
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};
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fsiack_clk: fsiack_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsiack";
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};
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fsibck_clk: fsibck_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsibck";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7740-cpg-clocks";
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reg = <0xe6150000 0x10000>;
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clocks = <&extal1_clk>, <&extalr_clk>;
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#clock-cells = <1>;
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clock-output-names = "system", "pllc0", "pllc1",
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"pllc2", "r",
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"usb24s",
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"i", "zg", "b", "m1", "hp",
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"hpp", "usbp", "s", "zb", "m3",
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"cp";
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};
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/* Variable factor clocks (DIV6) */
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sub_clk: sub_clk@e6150080 {
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compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150080 4>;
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clocks = <&pllc1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sub";
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};
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/* Fixed factor clocks */
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pllc1_div2_clk: pllc1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "pllc1_div2";
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};
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extal1_div2_clk: extal1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&extal1_clk>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "extal1_div2";
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};
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/* Gate clocks */
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subck_clks: subck_clks@e6150080 {
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compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150080 4>;
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clocks = <&sub_clk>, <&sub_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
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>;
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clock-output-names =
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"subck", "subck2";
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};
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mstp1_clks: mstp1_clks@e6150134 {
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compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150134 4>, <0xe6150038 4>;
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clocks = <&cpg_clocks R8A7740_CLK_S>,
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<&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
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<&cpg_clocks R8A7740_CLK_B>,
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<&sub_clk>, <&sub_clk>,
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<&cpg_clocks R8A7740_CLK_B>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
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R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
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R8A7740_CLK_LCDC0
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>;
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clock-output-names =
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"ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
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"tmu1", "lcdc0";
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};
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150138 4>, <0xe6150040 4>;
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clocks = <&sub_clk>, <&sub_clk>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
|
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<&cpg_clocks R8A7740_CLK_HP>,
|
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<&cpg_clocks R8A7740_CLK_HP>,
|
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<&sub_clk>, <&sub_clk>, <&sub_clk>,
|
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<&sub_clk>, <&sub_clk>, <&sub_clk>,
|
||||
<&sub_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
|
||||
R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
|
||||
R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
|
||||
R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
|
||||
R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
|
||||
R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
|
||||
R8A7740_CLK_SCIFA4
|
||||
>;
|
||||
clock-output-names =
|
||||
"scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
|
||||
"usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
|
||||
"scifa2", "scifa3", "scifa4";
|
||||
};
|
||||
mstp3_clks: mstp3_clks@e615013c {
|
||||
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0xe615013c 4>, <0xe6150048 4>;
|
||||
clocks = <&cpg_clocks R8A7740_CLK_R>,
|
||||
<&cpg_clocks R8A7740_CLK_HP>,
|
||||
<&sub_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_HP>,
|
||||
<&cpg_clocks R8A7740_CLK_HP>,
|
||||
<&cpg_clocks R8A7740_CLK_HP>,
|
||||
<&cpg_clocks R8A7740_CLK_HP>,
|
||||
<&cpg_clocks R8A7740_CLK_HP>,
|
||||
<&cpg_clocks R8A7740_CLK_HP>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
|
||||
R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
|
||||
R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
|
||||
>;
|
||||
clock-output-names =
|
||||
"cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
|
||||
"mmc", "gether", "tpu0";
|
||||
};
|
||||
mstp4_clks: mstp4_clks@e6150140 {
|
||||
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0xe6150140 4>, <0xe615004c 4>;
|
||||
clocks = <&cpg_clocks R8A7740_CLK_HP>,
|
||||
<&cpg_clocks R8A7740_CLK_HP>,
|
||||
<&cpg_clocks R8A7740_CLK_HP>,
|
||||
<&cpg_clocks R8A7740_CLK_HP>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7740_CLK_USBH R8A7740_CLK_SDHI2
|
||||
R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
|
||||
>;
|
||||
clock-output-names =
|
||||
"usbhost", "sdhi2", "usbfunc", "usphy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
|
@ -170,7 +171,7 @@ static void __init eva_init(void)
|
|||
l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
|
||||
#endif
|
||||
|
||||
r8a7740_add_standard_devices_dt();
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
r8a7740_pm_init();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -49,7 +49,6 @@ extern void r8a7740_init_irq_of(void);
|
|||
extern void r8a7740_map_io(void);
|
||||
extern void r8a7740_add_early_devices(void);
|
||||
extern void r8a7740_add_standard_devices(void);
|
||||
extern void r8a7740_add_standard_devices_dt(void);
|
||||
extern void r8a7740_clock_init(u8 md_ck);
|
||||
extern void r8a7740_pinmux_init(void);
|
||||
extern void r8a7740_pm_init(void);
|
||||
|
|
|
|||
|
|
@ -311,10 +311,6 @@ static struct platform_device ipmmu_device = {
|
|||
.num_resources = ARRAY_SIZE(ipmmu_resources),
|
||||
};
|
||||
|
||||
static struct platform_device *r8a7740_devices_dt[] __initdata = {
|
||||
&cmt1_device,
|
||||
};
|
||||
|
||||
static struct platform_device *r8a7740_early_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
|
|
@ -331,6 +327,7 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
|
|||
&irqpin3_device,
|
||||
&tmu0_device,
|
||||
&ipmmu_device,
|
||||
&cmt1_device,
|
||||
};
|
||||
|
||||
/* DMA */
|
||||
|
|
@ -756,8 +753,6 @@ void __init r8a7740_add_standard_devices(void)
|
|||
/* add devices */
|
||||
platform_add_devices(r8a7740_early_devices,
|
||||
ARRAY_SIZE(r8a7740_early_devices));
|
||||
platform_add_devices(r8a7740_devices_dt,
|
||||
ARRAY_SIZE(r8a7740_devices_dt));
|
||||
platform_add_devices(r8a7740_late_devices,
|
||||
ARRAY_SIZE(r8a7740_late_devices));
|
||||
|
||||
|
|
@ -779,8 +774,6 @@ void __init r8a7740_add_early_devices(void)
|
|||
{
|
||||
early_platform_add_devices(r8a7740_early_devices,
|
||||
ARRAY_SIZE(r8a7740_early_devices));
|
||||
early_platform_add_devices(r8a7740_devices_dt,
|
||||
ARRAY_SIZE(r8a7740_devices_dt));
|
||||
|
||||
/* setup early console here as well */
|
||||
shmobile_setup_console();
|
||||
|
|
@ -788,13 +781,6 @@ void __init r8a7740_add_early_devices(void)
|
|||
|
||||
#ifdef CONFIG_USE_OF
|
||||
|
||||
void __init r8a7740_add_standard_devices_dt(void)
|
||||
{
|
||||
platform_add_devices(r8a7740_devices_dt,
|
||||
ARRAY_SIZE(r8a7740_devices_dt));
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
void __init r8a7740_init_irq_of(void)
|
||||
{
|
||||
void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
|
||||
|
|
@ -828,7 +814,7 @@ void __init r8a7740_init_irq_of(void)
|
|||
static void __init r8a7740_generic_init(void)
|
||||
{
|
||||
r8a7740_clock_init(0);
|
||||
r8a7740_add_standard_devices_dt();
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char *r8a7740_boards_compat_dt[] __initdata = {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright 2014 Ulrich Hecht
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7740_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A7740_CLK_SYSTEM 0
|
||||
#define R8A7740_CLK_PLLC0 1
|
||||
#define R8A7740_CLK_PLLC1 2
|
||||
#define R8A7740_CLK_PLLC2 3
|
||||
#define R8A7740_CLK_R 4
|
||||
#define R8A7740_CLK_USB24S 5
|
||||
#define R8A7740_CLK_I 6
|
||||
#define R8A7740_CLK_ZG 7
|
||||
#define R8A7740_CLK_B 8
|
||||
#define R8A7740_CLK_M1 9
|
||||
#define R8A7740_CLK_HP 10
|
||||
#define R8A7740_CLK_HPP 11
|
||||
#define R8A7740_CLK_USBP 12
|
||||
#define R8A7740_CLK_S 13
|
||||
#define R8A7740_CLK_ZB 14
|
||||
#define R8A7740_CLK_M3 15
|
||||
#define R8A7740_CLK_CP 16
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7740_CLK_CEU21 28
|
||||
#define R8A7740_CLK_CEU20 27
|
||||
#define R8A7740_CLK_TMU0 25
|
||||
#define R8A7740_CLK_LCDC1 17
|
||||
#define R8A7740_CLK_IIC0 16
|
||||
#define R8A7740_CLK_TMU1 11
|
||||
#define R8A7740_CLK_LCDC0 0
|
||||
|
||||
/* MSTP2 */
|
||||
#define R8A7740_CLK_SCIFA6 30
|
||||
#define R8A7740_CLK_SCIFA7 22
|
||||
#define R8A7740_CLK_DMAC1 18
|
||||
#define R8A7740_CLK_DMAC2 17
|
||||
#define R8A7740_CLK_DMAC3 16
|
||||
#define R8A7740_CLK_USBDMAC 14
|
||||
#define R8A7740_CLK_SCIFA5 7
|
||||
#define R8A7740_CLK_SCIFB 6
|
||||
#define R8A7740_CLK_SCIFA0 4
|
||||
#define R8A7740_CLK_SCIFA1 3
|
||||
#define R8A7740_CLK_SCIFA2 2
|
||||
#define R8A7740_CLK_SCIFA3 1
|
||||
#define R8A7740_CLK_SCIFA4 0
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7740_CLK_CMT1 29
|
||||
#define R8A7740_CLK_FSI 28
|
||||
#define R8A7740_CLK_IIC1 23
|
||||
#define R8A7740_CLK_USBF 20
|
||||
#define R8A7740_CLK_SDHI0 14
|
||||
#define R8A7740_CLK_SDHI1 13
|
||||
#define R8A7740_CLK_MMC 12
|
||||
#define R8A7740_CLK_GETHER 9
|
||||
#define R8A7740_CLK_TPU0 4
|
||||
|
||||
/* MSTP4 */
|
||||
#define R8A7740_CLK_USBH 16
|
||||
#define R8A7740_CLK_SDHI2 15
|
||||
#define R8A7740_CLK_USBFUNC 7
|
||||
#define R8A7740_CLK_USBPHY 6
|
||||
|
||||
/* SUBCK* */
|
||||
#define R8A7740_CLK_SUBCK 9
|
||||
#define R8A7740_CLK_SUBCK2 10
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */
|
||||
Loading…
Reference in New Issue