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Documentation/memory-barriers.txt: Fix a typo in the data dependency description
This typo has been there forever, it is 7.5 years old, looks like this section of our memory ordering documentation is a place where most eyes are glazed over already ;-) [ Also fix some stray spaces and stray tabs while at it, shrinking the file by 49 bytes. Visual output unchanged. ] Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Link: http://lkml.kernel.org/n/tip-gncea9cb8igosblizfqMXrie@git.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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1 changed files with 21 additions and 21 deletions
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@ -500,7 +500,7 @@ odd-numbered bank is idle, one can see the new value of the pointer P (&B),
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but the old value of the variable B (2).
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but the old value of the variable B (2).
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Another example of where data dependency barriers might by required is where a
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Another example of where data dependency barriers might be required is where a
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number is read from memory and then used to calculate the index for an array
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number is read from memory and then used to calculate the index for an array
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access:
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access:
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@ -882,12 +882,12 @@ cache it for later use.
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Consider:
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Consider:
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CPU 1 CPU 2
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CPU 1 CPU 2
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======================= =======================
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======================= =======================
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LOAD B
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LOAD B
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DIVIDE } Divide instructions generally
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DIVIDE } Divide instructions generally
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DIVIDE } take a long time to perform
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DIVIDE } take a long time to perform
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LOAD A
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LOAD A
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Which might appear as this:
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Which might appear as this:
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@ -910,13 +910,13 @@ Which might appear as this:
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Placing a read barrier or a data dependency barrier just before the second
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Placing a read barrier or a data dependency barrier just before the second
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load:
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load:
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CPU 1 CPU 2
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CPU 1 CPU 2
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======================= =======================
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======================= =======================
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LOAD B
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LOAD B
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DIVIDE
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DIVIDE
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DIVIDE
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DIVIDE
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<read barrier>
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<read barrier>
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LOAD A
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LOAD A
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will force any value speculatively obtained to be reconsidered to an extent
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will force any value speculatively obtained to be reconsidered to an extent
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dependent on the type of barrier used. If there was no change made to the
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dependent on the type of barrier used. If there was no change made to the
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@ -1887,8 +1887,8 @@ functions:
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space should suffice for PCI.
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space should suffice for PCI.
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[*] NOTE! attempting to load from the same location as was written to may
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[*] NOTE! attempting to load from the same location as was written to may
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cause a malfunction - consider the 16550 Rx/Tx serial registers for
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cause a malfunction - consider the 16550 Rx/Tx serial registers for
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example.
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example.
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Used with prefetchable I/O memory, an mmiowb() barrier may be required to
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Used with prefetchable I/O memory, an mmiowb() barrier may be required to
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force stores to be ordered.
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force stores to be ordered.
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@ -1955,19 +1955,19 @@ barriers for the most part act at the interface between the CPU and its cache
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:
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:
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+--------+ +--------+ : +--------+ +-----------+
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+--------+ +--------+ : +--------+ +-----------+
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| | | | : | | | | +--------+
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| | | | : | | | | +--------+
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| CPU | | Memory | : | CPU | | | | |
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| CPU | | Memory | : | CPU | | | | |
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| Core |--->| Access |----->| Cache |<-->| | | |
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| Core |--->| Access |----->| Cache |<-->| | | |
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| | | Queue | : | | | |--->| Memory |
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| | | Queue | : | | | |--->| Memory |
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| | | | : | | | | | |
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| | | | : | | | | | |
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+--------+ +--------+ : +--------+ | | | |
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+--------+ +--------+ : +--------+ | | | |
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: | Cache | +--------+
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: | Cache | +--------+
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: | Coherency |
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: | Coherency |
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: | Mechanism | +--------+
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: | Mechanism | +--------+
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+--------+ +--------+ : +--------+ | | | |
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+--------+ +--------+ : +--------+ | | | |
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| | | | : | | | | | |
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| | | | : | | | | | |
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| CPU | | Memory | : | CPU | | |--->| Device |
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| CPU | | Memory | : | CPU | | |--->| Device |
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| Core |--->| Access |----->| Cache |<-->| | | |
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| Core |--->| Access |----->| Cache |<-->| | | |
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| | | Queue | : | | | | | |
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| | | Queue | : | | | | | |
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| | | | : | | | | +--------+
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| | | | : | | | | +--------+
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+--------+ +--------+ : +--------+ +-----------+
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+--------+ +--------+ : +--------+ +-----------+
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:
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:
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@ -2090,7 +2090,7 @@ CPU's caches by some other cache event:
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p = &v; q = p;
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p = &v; q = p;
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<D:request p>
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<D:request p>
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<B:modify p=&v> <D:commit p=&v>
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<B:modify p=&v> <D:commit p=&v>
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<D:read p>
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<D:read p>
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x = *q;
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x = *q;
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<C:read *q> Reads from v before v updated in cache
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<C:read *q> Reads from v before v updated in cache
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<C:unbusy>
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<C:unbusy>
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@ -2115,7 +2115,7 @@ queue before processing any further requests:
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p = &v; q = p;
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p = &v; q = p;
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<D:request p>
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<D:request p>
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<B:modify p=&v> <D:commit p=&v>
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<B:modify p=&v> <D:commit p=&v>
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<D:read p>
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<D:read p>
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smp_read_barrier_depends()
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smp_read_barrier_depends()
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<C:unbusy>
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<C:unbusy>
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<C:commit v=2>
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<C:commit v=2>
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