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KVM: riscv: selftests: Add smstateen registers to get-reg-list test
We have a new smstateen registers as separate sub-type of CSR ONE_REG interface so let us add these registers to get-reg-list test. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
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1 changed files with 34 additions and 0 deletions
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@ -36,6 +36,7 @@ bool filter_reg(__u64 reg)
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I:
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M:
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V:
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN:
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA:
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC:
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL:
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@ -186,6 +187,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id)
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"KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"
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#define RISCV_CSR_AIA(csr) \
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"KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"
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#define RISCV_CSR_SMSTATEEN(csr) \
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"KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"
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static const char *general_csr_id_to_str(__u64 reg_off)
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{
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@ -243,6 +246,18 @@ static const char *aia_csr_id_to_str(__u64 reg_off)
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return NULL;
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}
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static const char *smstateen_csr_id_to_str(__u64 reg_off)
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{
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/* reg_off is the offset into struct kvm_riscv_smstateen_csr */
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switch (reg_off) {
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case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0):
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return RISCV_CSR_SMSTATEEN(sstateen0);
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}
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TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off);
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return NULL;
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}
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static const char *csr_id_to_str(const char *prefix, __u64 id)
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{
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__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);
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@ -255,6 +270,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id)
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return general_csr_id_to_str(reg_off);
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case KVM_REG_RISCV_CSR_AIA:
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return aia_csr_id_to_str(reg_off);
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case KVM_REG_RISCV_CSR_SMSTATEEN:
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return smstateen_csr_id_to_str(reg_off);
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}
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TEST_FAIL("%s: Unknown csr subtype: 0x%llx", prefix, reg_subtype);
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@ -332,6 +349,7 @@ static const char *isa_ext_id_to_str(__u64 id)
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KVM_ISA_EXT_ARR(I),
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KVM_ISA_EXT_ARR(M),
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KVM_ISA_EXT_ARR(V),
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KVM_ISA_EXT_ARR(SMSTATEEN),
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KVM_ISA_EXT_ARR(SSAIA),
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KVM_ISA_EXT_ARR(SSTC),
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KVM_ISA_EXT_ARR(SVINVAL),
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@ -637,6 +655,11 @@ static __u64 aia_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA,
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};
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static __u64 smstateen_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0),
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN,
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};
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static __u64 fp_f_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]),
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KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]),
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@ -744,6 +767,8 @@ static __u64 fp_d_regs[] = {
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{"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),}
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#define AIA_REGS_SUBLIST \
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{"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}
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#define SMSTATEEN_REGS_SUBLIST \
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{"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}
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#define FP_F_REGS_SUBLIST \
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{"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \
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.regs_n = ARRAY_SIZE(fp_f_regs),}
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@ -871,6 +896,14 @@ static struct vcpu_reg_list aia_config = {
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},
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};
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static struct vcpu_reg_list smstateen_config = {
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.sublists = {
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BASE_SUBLIST,
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SMSTATEEN_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list fp_f_config = {
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.sublists = {
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BASE_SUBLIST,
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@ -903,6 +936,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
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&zifencei_config,
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&zihpm_config,
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&aia_config,
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&smstateen_config,
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&fp_f_config,
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&fp_d_config,
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};
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