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ARM: dts: r8a7740: use GIC_* defines
Use GIC_* defines for GIC interrupt cells in r8a7740 device tree. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Simon Horman
parent
4d5746a3ec
commit
e1e7b6fa83
1 changed files with 72 additions and 71 deletions
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@ -11,6 +11,7 @@
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/r8a7740-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@ -41,7 +42,7 @@ gic: interrupt-controller@c2800000 {
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xf0100000 0x1000>;
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interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&pd_a3sm>;
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arm,data-latency = <3 3 3>;
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arm,tag-latency = <2 2 2>;
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@ -58,7 +59,7 @@ dbsc3: memory-controller@fe400000 {
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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};
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ptm {
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@ -69,7 +70,7 @@ ptm {
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cmt1: timer@e6138000 {
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compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
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reg = <0xe6138000 0x170>;
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interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
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clock-names = "fck";
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power-domains = <&pd_c5>;
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@ -89,14 +90,14 @@ irqpin0: interrupt-controller@e6900000 {
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<0xe6900020 1>,
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<0xe6900040 1>,
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<0xe6900060 1>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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@ -111,14 +112,14 @@ irqpin1: interrupt-controller@e6900004 {
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<0xe6900024 1>,
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<0xe6900044 1>,
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<0xe6900064 1>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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@ -133,14 +134,14 @@ irqpin2: interrupt-controller@e6900008 {
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<0xe6900028 1>,
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<0xe6900048 1>,
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<0xe6900068 1>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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@ -155,14 +156,14 @@ irqpin3: interrupt-controller@e690000c {
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<0xe690002c 1>,
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<0xe690004c 1>,
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<0xe690006c 1>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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@ -171,7 +172,7 @@ ether: ethernet@e9a00000 {
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compatible = "renesas,gether-r8a7740";
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reg = <0xe9a00000 0x800>,
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<0xe9a01800 0x800>;
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interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
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power-domains = <&pd_a4s>;
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phy-mode = "mii";
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@ -185,10 +186,10 @@ i2c0: i2c@fff20000 {
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#size-cells = <0>;
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compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
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reg = <0xfff20000 0x425>;
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interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
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0 202 IRQ_TYPE_LEVEL_HIGH
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0 203 IRQ_TYPE_LEVEL_HIGH
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0 204 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
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power-domains = <&pd_a4r>;
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status = "disabled";
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@ -199,10 +200,10 @@ i2c1: i2c@e6c20000 {
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#size-cells = <0>;
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compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
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reg = <0xe6c20000 0x425>;
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interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
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0 71 IRQ_TYPE_LEVEL_HIGH
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0 72 IRQ_TYPE_LEVEL_HIGH
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0 73 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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@ -211,7 +212,7 @@ i2c1: i2c@e6c20000 {
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scifa0: serial@e6c40000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c40000 0x100>;
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interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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@ -221,7 +222,7 @@ scifa0: serial@e6c40000 {
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scifa1: serial@e6c50000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c50000 0x100>;
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interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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@ -231,7 +232,7 @@ scifa1: serial@e6c50000 {
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scifa2: serial@e6c60000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c60000 0x100>;
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interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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@ -241,7 +242,7 @@ scifa2: serial@e6c60000 {
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scifa3: serial@e6c70000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c70000 0x100>;
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interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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@ -251,7 +252,7 @@ scifa3: serial@e6c70000 {
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scifa4: serial@e6c80000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c80000 0x100>;
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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@ -261,7 +262,7 @@ scifa4: serial@e6c80000 {
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scifa5: serial@e6cb0000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6cb0000 0x100>;
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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@ -271,7 +272,7 @@ scifa5: serial@e6cb0000 {
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scifa6: serial@e6cc0000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6cc0000 0x100>;
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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@ -281,7 +282,7 @@ scifa6: serial@e6cc0000 {
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scifa7: serial@e6cd0000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6cd0000 0x100>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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@ -291,7 +292,7 @@ scifa7: serial@e6cd0000 {
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scifb: serial@e6c30000 {
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compatible = "renesas,scifb-r8a7740", "renesas,scifb";
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reg = <0xe6c30000 0x100>;
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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@ -329,8 +330,8 @@ tpu: pwm@e6600000 {
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mmcif0: mmc@e6bd0000 {
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compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
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reg = <0xe6bd0000 0x100>;
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interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
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0 57 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_MMC>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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@ -339,9 +340,9 @@ mmcif0: mmc@e6bd0000 {
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sdhi0: sd@e6850000 {
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xe6850000 0x100>;
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interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
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0 118 IRQ_TYPE_LEVEL_HIGH
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0 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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@ -352,9 +353,9 @@ sdhi0: sd@e6850000 {
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sdhi1: sd@e6860000 {
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xe6860000 0x100>;
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interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
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0 122 IRQ_TYPE_LEVEL_HIGH
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0 123 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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@ -365,9 +366,9 @@ sdhi1: sd@e6860000 {
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sdhi2: sd@e6870000 {
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xe6870000 0x100>;
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interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
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0 126 IRQ_TYPE_LEVEL_HIGH
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0 127 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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@ -379,7 +380,7 @@ sh_fsi2: sound@fe1f0000 {
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#sound-dai-cells = <1>;
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compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
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reg = <0xfe1f0000 0x400>;
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interrupts = <0 9 0x4>;
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interrupts = <GIC_SPI 9 0x4>;
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clocks = <&mstp3_clks R8A7740_CLK_FSI>;
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power-domains = <&pd_a4mp>;
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status = "disabled";
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@ -388,9 +389,9 @@ sh_fsi2: sound@fe1f0000 {
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tmu0: timer@fff80000 {
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compatible = "renesas,tmu-r8a7740", "renesas,tmu";
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reg = <0xfff80000 0x2c>;
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interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
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<0 199 IRQ_TYPE_LEVEL_HIGH>,
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<0 200 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
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clock-names = "fck";
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power-domains = <&pd_a4r>;
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@ -403,9 +404,9 @@ tmu0: timer@fff80000 {
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tmu1: timer@fff90000 {
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compatible = "renesas,tmu-r8a7740", "renesas,tmu";
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reg = <0xfff90000 0x2c>;
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interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>,
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<0 171 IRQ_TYPE_LEVEL_HIGH>,
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<0 172 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
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clock-names = "fck";
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power-domains = <&pd_a4r>;
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