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dt-bindings: clock: qcom: add misc resets for PCIE and NSS

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PCIE and NSS has MISC reset register in which single register has
multiple reset bit. The patch adds the DT bindings for these MISC
resets.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Abhishek Sahu 2017-12-13 19:55:41 +05:30 committed by Stephen Boyd
parent 033c9b96b2
commit e1f34e4f27
1 changed files with 42 additions and 0 deletions
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42
include/dt-bindings/clock/qcom,gcc-ipq8074.h
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@ -328,5 +328,47 @@
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86
#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87
#define GCC_SMMU_CATS_BCR 88
#define GCC_UBI0_AXI_ARES 89
#define GCC_UBI0_AHB_ARES 90
#define GCC_UBI0_NC_AXI_ARES 91
#define GCC_UBI0_DBG_ARES 92
#define GCC_UBI0_CORE_CLAMP_ENABLE 93
#define GCC_UBI0_CLKRST_CLAMP_ENABLE 94
#define GCC_UBI1_AXI_ARES 95
#define GCC_UBI1_AHB_ARES 96
#define GCC_UBI1_NC_AXI_ARES 97
#define GCC_UBI1_DBG_ARES 98
#define GCC_UBI1_CORE_CLAMP_ENABLE 99
#define GCC_UBI1_CLKRST_CLAMP_ENABLE 100
#define GCC_NSS_CFG_ARES 101
#define GCC_NSS_IMEM_ARES 102
#define GCC_NSS_NOC_ARES 103
#define GCC_NSS_CRYPTO_ARES 104
#define GCC_NSS_CSR_ARES 105
#define GCC_NSS_CE_APB_ARES 106
#define GCC_NSS_CE_AXI_ARES 107
#define GCC_NSSNOC_CE_APB_ARES 108
#define GCC_NSSNOC_CE_AXI_ARES 109
#define GCC_NSSNOC_UBI0_AHB_ARES 110
#define GCC_NSSNOC_UBI1_AHB_ARES 111
#define GCC_NSSNOC_SNOC_ARES 112
#define GCC_NSSNOC_CRYPTO_ARES 113
#define GCC_NSSNOC_ATB_ARES 114
#define GCC_NSSNOC_QOSGEN_REF_ARES 115
#define GCC_NSSNOC_TIMEOUT_REF_ARES 116
#define GCC_PCIE0_PIPE_ARES 117
#define GCC_PCIE0_SLEEP_ARES 118
#define GCC_PCIE0_CORE_STICKY_ARES 119
#define GCC_PCIE0_AXI_MASTER_ARES 120
#define GCC_PCIE0_AXI_SLAVE_ARES 121
#define GCC_PCIE0_AHB_ARES 122
#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123
#define GCC_PCIE1_PIPE_ARES 124
#define GCC_PCIE1_SLEEP_ARES 125
#define GCC_PCIE1_CORE_STICKY_ARES 126
#define GCC_PCIE1_AXI_MASTER_ARES 127
#define GCC_PCIE1_AXI_SLAVE_ARES 128
#define GCC_PCIE1_AHB_ARES 129
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#endif