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[ARM] S3C24XX: Split pll code out of regs-clock.h
Move the PLL calculation code into it's own header file for re-use with the other plat-s3c24xx based systems such as the S3C24A0. Note, we change the name of s3c2410_get_pll to the more generically named s3c24xx_get_pll as well as the related defintions. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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93bc6b6371
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7 changed files with 49 additions and 41 deletions
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@ -42,13 +42,6 @@
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#define S3C2410_CLKCON_IIS (1<<17)
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#define S3C2410_CLKCON_SPI (1<<18)
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#define S3C2410_PLLCON_MDIVSHIFT 12
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#define S3C2410_PLLCON_PDIVSHIFT 4
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#define S3C2410_PLLCON_SDIVSHIFT 0
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#define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
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#define S3C2410_PLLCON_PDIVMASK ((1<<5)-1)
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#define S3C2410_PLLCON_SDIVMASK 3
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/* DCLKCON register addresses in gpio.h */
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#define S3C2410_DCLKCON_DCLK0EN (1<<0)
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@ -76,32 +69,6 @@
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#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
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#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
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#ifndef __ASSEMBLY__
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#include <asm/div64.h>
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static inline unsigned int
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s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
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{
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unsigned int mdiv, pdiv, sdiv;
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uint64_t fvco;
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mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
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pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
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sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
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mdiv &= S3C2410_PLLCON_MDIVMASK;
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pdiv &= S3C2410_PLLCON_PDIVMASK;
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sdiv &= S3C2410_PLLCON_SDIVMASK;
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fvco = (uint64_t)baseclk * (mdiv + 8);
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do_div(fvco, (pdiv + 2) << sdiv);
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return (unsigned int)fvco;
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}
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#endif /* __ASSEMBLY__ */
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#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
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/* extra registers */
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@ -43,6 +43,7 @@
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#include <plat/clock.h>
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#include <plat/devs.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/pm.h>
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static struct map_desc h1940_iodesc[] __initdata = {
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@ -223,10 +224,9 @@ static void __init h1940_init(void)
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S3C2410_MISCCR_USBSUSPND0 |
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S3C2410_MISCCR_USBSUSPND1, 0x0);
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tmp = (
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0x78 << S3C2410_PLLCON_MDIVSHIFT)
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| (0x02 << S3C2410_PLLCON_PDIVSHIFT)
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| (0x03 << S3C2410_PLLCON_SDIVSHIFT);
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tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
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| (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
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| (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
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writel(tmp, S3C2410_UPLLCON);
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platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
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@ -35,6 +35,7 @@
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/clock.h>
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#include <plat/pll.h>
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/* Initial IO mappings */
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@ -74,7 +75,7 @@ void __init s3c2410_init_clocks(int xtal)
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/* now we've got our machine bits initialised, work out what
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* clocks we've got */
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fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
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fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
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tmp = __raw_readl(S3C2410_CLKDIVN);
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@ -47,6 +47,7 @@
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#include <plat/devs.h>
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#include <plat/clock.h>
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#include <plat/pm.h>
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#include <plat/pll.h>
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#ifndef CONFIG_CPU_S3C2412_ONLY
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void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
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@ -165,7 +166,7 @@ void __init s3c2412_init_clocks(int xtal)
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/* now we've got our machine bits initialised, work out what
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* clocks we've got */
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fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
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fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
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clk_mpll.rate = fclk;
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@ -49,6 +49,7 @@
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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/* clock information */
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@ -332,7 +333,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
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/* initialise the main system clocks */
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clk_xtal.rate = xtal;
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clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
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clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
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clk_mpll.rate = fclk;
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clk_h.rate = hclk;
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37
arch/arm/plat-s3c24xx/include/plat/pll.h
Normal file
37
arch/arm/plat-s3c24xx/include/plat/pll.h
Normal file
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@ -0,0 +1,37 @@
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/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
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*
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C24xx - common pll registers and code
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*/
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#define S3C24XX_PLLCON_MDIVSHIFT 12
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#define S3C24XX_PLLCON_PDIVSHIFT 4
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#define S3C24XX_PLLCON_SDIVSHIFT 0
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#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
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#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1)
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#define S3C24XX_PLLCON_SDIVMASK 3
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#include <asm/div64.h>
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static inline unsigned int
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s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
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{
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unsigned int mdiv, pdiv, sdiv;
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uint64_t fvco;
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mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
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pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
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sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
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mdiv &= S3C24XX_PLLCON_MDIVMASK;
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pdiv &= S3C24XX_PLLCON_PDIVMASK;
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sdiv &= S3C24XX_PLLCON_SDIVMASK;
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fvco = (uint64_t)baseclk * (mdiv + 8);
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do_div(fvco, (pdiv + 2) << sdiv);
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return (unsigned int)fvco;
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}
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@ -42,6 +42,7 @@
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#include <plat/devs.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/pll.h>
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static struct map_desc s3c244x_iodesc[] __initdata = {
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IODESC_ENT(CLKPWR),
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@ -80,7 +81,7 @@ void __init s3c244x_init_clocks(int xtal)
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/* now we've got our machine bits initialised, work out what
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* clocks we've got */
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fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
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fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
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clkdiv = __raw_readl(S3C2410_CLKDIVN);
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camdiv = __raw_readl(S3C2440_CAMDIVN);
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