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clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
[ Upstream commitf167675486
] The current code defines W1 clock gate to be at 0x1cc, overlaying it with the IR gate. Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver causing interrupt floods on H6 (because interrupt flags can't be cleared, due to IR module's bus being disabled). Fixes:b7c7b05065
("clk: sunxi-ng: add support for H6 PRCM CCU") Signed-off-by: Ondrej Jirman <megous@megous.com> Acked-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
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static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
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0x1cc, BIT(0), 0);
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static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
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0x1cc, BIT(0), 0);
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0x1ec, BIT(0), 0);
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/* Information of IR(RX) mod clock is gathered from BSP source code */
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static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
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