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mlxsw: reg: Extend MFDE register with new events and parameters
Extend the Monitoring Firmware Debug (MFDE) register with new events and their related parameters. These events will be utilized by devlink-health in the next patch. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Danielle Ratson
David S. Miller
parent
4bcbf50291
commit
e25c060c5f
1 changed files with 104 additions and 1 deletions
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@ -11318,7 +11318,7 @@ mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
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* -----------------------------------
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*/
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#define MLXSW_REG_MFDE_ID 0x9200
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#define MLXSW_REG_MFDE_LEN 0x18
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#define MLXSW_REG_MFDE_LEN 0x30
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MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN);
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@ -11328,10 +11328,32 @@ MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN);
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*/
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MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8);
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enum mlxsw_reg_mfde_severity {
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/* Unrecoverable switch behavior */
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MLXSW_REG_MFDE_SEVERITY_FATL = 2,
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/* Unexpected state with possible systemic failure */
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MLXSW_REG_MFDE_SEVERITY_NRML = 3,
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/* Unexpected state without systemic failure */
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MLXSW_REG_MFDE_SEVERITY_INTR = 5,
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};
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/* reg_mfde_severity
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* The severity of the event.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8);
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enum mlxsw_reg_mfde_event_id {
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/* CRspace timeout */
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MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1,
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/* KVD insertion machine stopped */
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MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP,
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/* Triggered by MFGD.trigger_test */
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MLXSW_REG_MFDE_EVENT_ID_TEST,
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/* Triggered when firmware hits an assert */
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MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT,
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/* Fatal error interrupt from hardware */
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MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE,
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};
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/* reg_mfde_event_id
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@ -11378,6 +11400,13 @@ MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16);
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*/
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MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32);
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/* reg_mfde_crspace_to_oe
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* 0 - New event
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* 1 - Old event, occurred before MFGD activation.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1);
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/* reg_mfde_crspace_to_log_id
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* Which irisc triggered the timeout.
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* Access: RO
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@ -11390,12 +11419,86 @@ MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4);
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*/
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MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64);
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/* reg_mfde_kvd_im_stop_oe
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* 0 - New event
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* 1 - Old event, occurred before MFGD activation.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1);
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/* reg_mfde_kvd_im_stop_pipes_mask
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* Bit per kvh pipe.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16);
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/* reg_mfde_fw_assert_var0-4
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* Variables passed to assert.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32);
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MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32);
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MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32);
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MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32);
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MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32);
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/* reg_mfde_fw_assert_existptr
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* The instruction pointer when assert was triggered.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32);
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/* reg_mfde_fw_assert_callra
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* The return address after triggering assert.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32);
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/* reg_mfde_fw_assert_oe
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* 0 - New event
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* 1 - Old event, occurred before MFGD activation.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1);
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/* reg_mfde_fw_assert_tile_v
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* 0: The assert was from main
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* 1: The assert was from a tile
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1);
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/* reg_mfde_fw_assert_tile_index
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* When tile_v=1, the tile_index that caused the assert.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6);
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/* reg_mfde_fw_assert_ext_synd
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* A generated one-to-one identifier which is specific per-assert.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16);
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/* reg_mfde_fatal_cause_id
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* HW interrupt cause id.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18);
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/* reg_mfde_fatal_cause_tile_v
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* 0: The assert was from main
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* 1: The assert was from a tile
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1);
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/* reg_mfde_fatal_cause_tile_index
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* When tile_v=1, the tile_index that caused the assert.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6);
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/* TNGCR - Tunneling NVE General Configuration Register
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* ----------------------------------------------------
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* The TNGCR register is used for setting up the NVE Tunneling configuration.
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