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mtd: fsmc_nand: Add BCH4 SW ECC support for SPEAr600
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can be used by boards equipped with a NAND chip that requires 4-bit ECC strength. The SPEAr600 HW ECC only supports 1-bit ECC strength. To enable SW BCH4, you need to specify this in your nand controller DT node: nand-ecc-mode = "soft_bch"; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; Tested on a custom SPEAr600 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> [Brian: tweaked the comments a bit] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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parent
48c25cf441
commit
e278fc71b2
2 changed files with 47 additions and 16 deletions
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@ -30,6 +30,12 @@ Optional properties:
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command is asserted. Zero means one cycle, 255 means 256
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cycles.
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- bank: default NAND bank to use (0-3 are valid, 0 is the default).
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- nand-ecc-mode : see nand.txt
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- nand-ecc-strength : see nand.txt
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- nand-ecc-step-size : see nand.txt
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Can support 1-bit HW ECC (default) or if stronger correction is required,
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software-based BCH.
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Example:
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@ -1023,12 +1023,17 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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nand->cmd_ctrl = fsmc_cmd_ctrl;
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nand->chip_delay = 30;
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/*
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* Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
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* can overwrite this value if the DT provides a different value.
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*/
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.hwctl = fsmc_enable_hwecc;
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nand->ecc.size = 512;
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nand->options = pdata->options;
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nand->select_chip = fsmc_select_chip;
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nand->badblockbits = 7;
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nand->flash_node = np;
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if (pdata->width == FSMC_NAND_BW16)
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nand->options |= NAND_BUSWIDTH_16;
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@ -1070,11 +1075,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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nand->ecc.correct = fsmc_bch8_correct_data;
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nand->ecc.bytes = 13;
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nand->ecc.strength = 8;
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} else {
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nand->ecc.calculate = fsmc_read_hwecc_ecc1;
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nand->ecc.correct = nand_correct_data;
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nand->ecc.bytes = 3;
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nand->ecc.strength = 1;
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}
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/*
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@ -1115,22 +1115,47 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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goto err_probe;
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}
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} else {
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switch (host->mtd.oobsize) {
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case 16:
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nand->ecc.layout = &fsmc_ecc1_16_layout;
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switch (nand->ecc.mode) {
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case NAND_ECC_HW:
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dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
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nand->ecc.calculate = fsmc_read_hwecc_ecc1;
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nand->ecc.correct = nand_correct_data;
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nand->ecc.bytes = 3;
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nand->ecc.strength = 1;
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break;
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case 64:
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nand->ecc.layout = &fsmc_ecc1_64_layout;
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break;
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case 128:
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nand->ecc.layout = &fsmc_ecc1_128_layout;
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case NAND_ECC_SOFT_BCH:
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dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
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break;
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default:
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dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
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mtd->oobsize);
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ret = -EINVAL;
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dev_err(&pdev->dev, "Unsupported ECC mode!\n");
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goto err_probe;
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}
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/*
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* Don't set layout for BCH4 SW ECC. This will be
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* generated later in nand_bch_init() later.
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*/
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if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {
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switch (host->mtd.oobsize) {
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case 16:
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nand->ecc.layout = &fsmc_ecc1_16_layout;
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break;
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case 64:
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nand->ecc.layout = &fsmc_ecc1_64_layout;
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break;
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case 128:
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nand->ecc.layout = &fsmc_ecc1_128_layout;
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break;
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default:
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dev_warn(&pdev->dev,
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"No oob scheme defined for oobsize %d\n",
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mtd->oobsize);
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ret = -EINVAL;
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goto err_probe;
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}
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}
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}
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/* Second stage of scan to fill MTD data-structures */
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