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watchdog: dw: RMW the control register
[ Upstream commit a81abbb412
]
RK3399 has rst_pulse_length in CONTROL_REG[4:2], determining the length
of pulse to issue for system reset. We shouldn't clobber this value,
because that might make the system reset ineffective. On RK3399, we're
seeing that a value of 000b (meaning 2 cycles) yields an unreliable
(partial?) reset, and so we only fully reset after the watchdog fires a
second time. If we retain the system default (010b, or 8 clock cycles),
then the watchdog reset is much more reliable.
Read-modify-write retains the system value and improves reset
reliability.
It seems we were intentionally clobbering the response mode previously,
to ensure we performed a system reset (we don't support an interrupt
notification), so retain that explicitly.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
e2b3fa0ce9
commit
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1 changed files with 15 additions and 8 deletions
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@ -34,6 +34,7 @@
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#define WDOG_CONTROL_REG_OFFSET 0x00
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#define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
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#define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02
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#define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
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#define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4
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#define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
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@ -121,14 +122,23 @@ static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
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return 0;
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}
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static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
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{
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u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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/* Disable interrupt mode; always perform system reset. */
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val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
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/* Enable watchdog. */
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val |= WDOG_CONTROL_REG_WDT_EN_MASK;
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writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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}
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static int dw_wdt_start(struct watchdog_device *wdd)
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{
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struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
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dw_wdt_set_timeout(wdd, wdd->timeout);
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writel(WDOG_CONTROL_REG_WDT_EN_MASK,
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dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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dw_wdt_arm_system_reset(dw_wdt);
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return 0;
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}
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@ -152,16 +162,13 @@ static int dw_wdt_restart(struct watchdog_device *wdd,
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unsigned long action, void *data)
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{
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struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
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u32 val;
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writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
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val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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if (val & WDOG_CONTROL_REG_WDT_EN_MASK)
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if (dw_wdt_is_enabled(dw_wdt))
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writel(WDOG_COUNTER_RESTART_KICK_VALUE,
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dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
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else
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writel(WDOG_CONTROL_REG_WDT_EN_MASK,
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dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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dw_wdt_arm_system_reset(dw_wdt);
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/* wait for reset to assert... */
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mdelay(500);
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