clk: mediatek: Add MT2712 clock support
Add MT2712 clock support, include topckgen, apmixedsys, infracfg, pericfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> [sboyd@codeaurora.org: Static on top_clk_data] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
weiyi.lu@mediatek.com
Stephen Boyd
parent
b7f1a721bb
commit
e2f744a82d
|
|
@ -50,6 +50,56 @@ config COMMON_CLK_MT2701_BDPSYS
|
|||
---help---
|
||||
This driver supports Mediatek MT2701 bdpsys clocks.
|
||||
|
||||
config COMMON_CLK_MT2712
|
||||
bool "Clock driver for Mediatek MT2712"
|
||||
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
|
||||
select COMMON_CLK_MEDIATEK
|
||||
default ARCH_MEDIATEK && ARM64
|
||||
---help---
|
||||
This driver supports Mediatek MT2712 basic clocks.
|
||||
|
||||
config COMMON_CLK_MT2712_BDPSYS
|
||||
bool "Clock driver for Mediatek MT2712 bdpsys"
|
||||
depends on COMMON_CLK_MT2712
|
||||
---help---
|
||||
This driver supports Mediatek MT2712 bdpsys clocks.
|
||||
|
||||
config COMMON_CLK_MT2712_IMGSYS
|
||||
bool "Clock driver for Mediatek MT2712 imgsys"
|
||||
depends on COMMON_CLK_MT2712
|
||||
---help---
|
||||
This driver supports Mediatek MT2712 imgsys clocks.
|
||||
|
||||
config COMMON_CLK_MT2712_JPGDECSYS
|
||||
bool "Clock driver for Mediatek MT2712 jpgdecsys"
|
||||
depends on COMMON_CLK_MT2712
|
||||
---help---
|
||||
This driver supports Mediatek MT2712 jpgdecsys clocks.
|
||||
|
||||
config COMMON_CLK_MT2712_MFGCFG
|
||||
bool "Clock driver for Mediatek MT2712 mfgcfg"
|
||||
depends on COMMON_CLK_MT2712
|
||||
---help---
|
||||
This driver supports Mediatek MT2712 mfgcfg clocks.
|
||||
|
||||
config COMMON_CLK_MT2712_MMSYS
|
||||
bool "Clock driver for Mediatek MT2712 mmsys"
|
||||
depends on COMMON_CLK_MT2712
|
||||
---help---
|
||||
This driver supports Mediatek MT2712 mmsys clocks.
|
||||
|
||||
config COMMON_CLK_MT2712_VDECSYS
|
||||
bool "Clock driver for Mediatek MT2712 vdecsys"
|
||||
depends on COMMON_CLK_MT2712
|
||||
---help---
|
||||
This driver supports Mediatek MT2712 vdecsys clocks.
|
||||
|
||||
config COMMON_CLK_MT2712_VENCSYS
|
||||
bool "Clock driver for Mediatek MT2712 vencsys"
|
||||
depends on COMMON_CLK_MT2712
|
||||
---help---
|
||||
This driver supports Mediatek MT2712 vencsys clocks.
|
||||
|
||||
config COMMON_CLK_MT6797
|
||||
bool "Clock driver for Mediatek MT6797"
|
||||
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
|
||||
|
|
|
|||
|
|
@ -12,5 +12,13 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
|
|||
obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs bdp_cg_regs = {
|
||||
.set_ofs = 0x100,
|
||||
.clr_ofs = 0x100,
|
||||
.sta_ofs = 0x100,
|
||||
};
|
||||
|
||||
#define GATE_BDP(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &bdp_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate bdp_clks[] = {
|
||||
GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
|
||||
GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
|
||||
GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
|
||||
GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
|
||||
GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
|
||||
GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
|
||||
GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
|
||||
GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
|
||||
GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
|
||||
GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
|
||||
GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
|
||||
GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
|
||||
GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
|
||||
GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
|
||||
GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
|
||||
GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
|
||||
};
|
||||
|
||||
static int clk_mt2712_bdp_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_bdp[] = {
|
||||
{ .compatible = "mediatek,mt2712-bdpsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_bdp_drv = {
|
||||
.probe = clk_mt2712_bdp_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-bdp",
|
||||
.of_match_table = of_match_clk_mt2712_bdp,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_bdp_drv);
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs img_cg_regs = {
|
||||
.set_ofs = 0x0,
|
||||
.clr_ofs = 0x0,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_IMG(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &img_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate img_clks[] = {
|
||||
GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0),
|
||||
GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3),
|
||||
GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8),
|
||||
GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9),
|
||||
GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10),
|
||||
GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11),
|
||||
};
|
||||
|
||||
static int clk_mt2712_img_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_img[] = {
|
||||
{ .compatible = "mediatek,mt2712-imgsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_img_drv = {
|
||||
.probe = clk_mt2712_img_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-img",
|
||||
.of_match_table = of_match_clk_mt2712_img,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_img_drv);
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs jpgdec_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_JPGDEC(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &jpgdec_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate jpgdec_clks[] = {
|
||||
GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0),
|
||||
GATE_JPGDEC(CLK_JPGDEC_JPGDEC, "jpgdec_jpgdec", "jpgdec_sel", 4),
|
||||
};
|
||||
|
||||
static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_JPGDEC_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_jpgdec[] = {
|
||||
{ .compatible = "mediatek,mt2712-jpgdecsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_jpgdec_drv = {
|
||||
.probe = clk_mt2712_jpgdec_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-jpgdec",
|
||||
.of_match_table = of_match_clk_mt2712_jpgdec,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_jpgdec_drv);
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs mfg_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_MFG(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mfg_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate mfg_clks[] = {
|
||||
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
|
||||
};
|
||||
|
||||
static int clk_mt2712_mfg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_mfg[] = {
|
||||
{ .compatible = "mediatek,mt2712-mfgcfg", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_mfg_drv = {
|
||||
.probe = clk_mt2712_mfg_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-mfg",
|
||||
.of_match_table = of_match_clk_mt2712_mfg,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_mfg_drv);
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs mm0_cg_regs = {
|
||||
.set_ofs = 0x104,
|
||||
.clr_ofs = 0x108,
|
||||
.sta_ofs = 0x100,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs mm1_cg_regs = {
|
||||
.set_ofs = 0x114,
|
||||
.clr_ofs = 0x118,
|
||||
.sta_ofs = 0x110,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs mm2_cg_regs = {
|
||||
.set_ofs = 0x224,
|
||||
.clr_ofs = 0x228,
|
||||
.sta_ofs = 0x220,
|
||||
};
|
||||
|
||||
#define GATE_MM0(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mm0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_MM1(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mm1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_MM2(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mm2_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate mm_clks[] = {
|
||||
/* MM0 */
|
||||
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
|
||||
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
|
||||
GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
|
||||
GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
|
||||
GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
|
||||
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
|
||||
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
|
||||
GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
|
||||
GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
|
||||
GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
|
||||
GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
|
||||
GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
|
||||
GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
|
||||
GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
|
||||
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
|
||||
GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
|
||||
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
|
||||
GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
|
||||
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
|
||||
GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
|
||||
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
|
||||
GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
|
||||
GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
|
||||
GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
|
||||
GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
|
||||
GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
|
||||
GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
|
||||
/* MM1 */
|
||||
GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
|
||||
GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),
|
||||
GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),
|
||||
GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),
|
||||
GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
|
||||
GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),
|
||||
GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
|
||||
GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),
|
||||
GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),
|
||||
GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
|
||||
GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),
|
||||
GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
|
||||
GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),
|
||||
GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),
|
||||
GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
|
||||
GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),
|
||||
GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),
|
||||
GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),
|
||||
GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),
|
||||
GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),
|
||||
GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),
|
||||
GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),
|
||||
GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),
|
||||
GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),
|
||||
GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),
|
||||
GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),
|
||||
/* MM2 */
|
||||
GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),
|
||||
GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),
|
||||
GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),
|
||||
GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),
|
||||
GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),
|
||||
GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),
|
||||
GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),
|
||||
};
|
||||
|
||||
static int clk_mt2712_mm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_mm[] = {
|
||||
{ .compatible = "mediatek,mt2712-mmsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_mm_drv = {
|
||||
.probe = clk_mt2712_mm_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-mm",
|
||||
.of_match_table = of_match_clk_mt2712_mm,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_mm_drv);
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs vdec0_cg_regs = {
|
||||
.set_ofs = 0x0,
|
||||
.clr_ofs = 0x4,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs vdec1_cg_regs = {
|
||||
.set_ofs = 0x8,
|
||||
.clr_ofs = 0xc,
|
||||
.sta_ofs = 0x8,
|
||||
};
|
||||
|
||||
#define GATE_VDEC0(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &vdec0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr_inv, \
|
||||
}
|
||||
|
||||
#define GATE_VDEC1(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &vdec1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate vdec_clks[] = {
|
||||
/* VDEC0 */
|
||||
GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
|
||||
/* VDEC1 */
|
||||
GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
|
||||
GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
|
||||
};
|
||||
|
||||
static int clk_mt2712_vdec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_vdec[] = {
|
||||
{ .compatible = "mediatek,mt2712-vdecsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_vdec_drv = {
|
||||
.probe = clk_mt2712_vdec_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-vdec",
|
||||
.of_match_table = of_match_clk_mt2712_vdec,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_vdec_drv);
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs venc_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_VENC(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &venc_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate venc_clks[] = {
|
||||
GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0),
|
||||
GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
|
||||
GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12),
|
||||
};
|
||||
|
||||
static int clk_mt2712_venc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_venc[] = {
|
||||
{ .compatible = "mediatek,mt2712-vencsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_venc_drv = {
|
||||
.probe = clk_mt2712_venc_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-venc",
|
||||
.of_match_table = of_match_clk_mt2712_venc,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_venc_drv);
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -207,6 +207,8 @@ struct mtk_pll_data {
|
|||
uint32_t en_mask;
|
||||
uint32_t pd_reg;
|
||||
uint32_t tuner_reg;
|
||||
uint32_t tuner_en_reg;
|
||||
uint8_t tuner_en_bit;
|
||||
int pd_shift;
|
||||
unsigned int flags;
|
||||
const struct clk_ops *ops;
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ struct mtk_clk_pll {
|
|||
void __iomem *pd_addr;
|
||||
void __iomem *pwr_addr;
|
||||
void __iomem *tuner_addr;
|
||||
void __iomem *tuner_en_addr;
|
||||
void __iomem *pcw_addr;
|
||||
const struct mtk_pll_data *data;
|
||||
};
|
||||
|
|
@ -227,7 +228,10 @@ static int mtk_pll_prepare(struct clk_hw *hw)
|
|||
r |= pll->data->en_mask;
|
||||
writel(r, pll->base_addr + REG_CON0);
|
||||
|
||||
if (pll->tuner_addr) {
|
||||
if (pll->tuner_en_addr) {
|
||||
r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
|
||||
writel(r, pll->tuner_en_addr);
|
||||
} else if (pll->tuner_addr) {
|
||||
r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
|
||||
writel(r, pll->tuner_addr);
|
||||
}
|
||||
|
|
@ -254,7 +258,10 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
|
|||
writel(r, pll->base_addr + REG_CON0);
|
||||
}
|
||||
|
||||
if (pll->tuner_addr) {
|
||||
if (pll->tuner_en_addr) {
|
||||
r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
|
||||
writel(r, pll->tuner_en_addr);
|
||||
} else if (pll->tuner_addr) {
|
||||
r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
|
||||
writel(r, pll->tuner_addr);
|
||||
}
|
||||
|
|
@ -297,6 +304,8 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
|
|||
pll->pcw_addr = base + data->pcw_reg;
|
||||
if (data->tuner_reg)
|
||||
pll->tuner_addr = base + data->tuner_reg;
|
||||
if (data->tuner_en_reg)
|
||||
pll->tuner_en_addr = base + data->tuner_en_reg;
|
||||
pll->hw.init = &init;
|
||||
pll->data = data;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue