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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-05 08:26:59 +00:00
drm/i915/gvt: Add KBL dispatch logic in each function.
Extend function dispatch logic to support KBL platform. Signed-off-by: Xu Han <xu.han@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
parent
6f696d1355
commit
e3476c0021
8 changed files with 43 additions and 26 deletions
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@ -1215,7 +1215,7 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s,
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if (!info->async_flip)
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if (!info->async_flip)
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return 0;
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return 0;
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if (IS_SKYLAKE(dev_priv)) {
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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stride = vgpu_vreg(s->vgpu, info->stride_reg) & GENMASK(9, 0);
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stride = vgpu_vreg(s->vgpu, info->stride_reg) & GENMASK(9, 0);
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tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) &
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tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) &
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GENMASK(12, 10)) >> 10;
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GENMASK(12, 10)) >> 10;
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@ -1243,7 +1243,7 @@ static int gen8_update_plane_mmio_from_mi_display_flip(
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set_mask_bits(&vgpu_vreg(vgpu, info->surf_reg), GENMASK(31, 12),
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set_mask_bits(&vgpu_vreg(vgpu, info->surf_reg), GENMASK(31, 12),
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info->surf_val << 12);
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info->surf_val << 12);
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if (IS_SKYLAKE(dev_priv)) {
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(9, 0),
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set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(9, 0),
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info->stride_val);
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info->stride_val);
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set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(12, 10),
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set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(12, 10),
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@ -1267,7 +1267,7 @@ static int decode_mi_display_flip(struct parser_exec_state *s,
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if (IS_BROADWELL(dev_priv))
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if (IS_BROADWELL(dev_priv))
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return gen8_decode_mi_display_flip(s, info);
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return gen8_decode_mi_display_flip(s, info);
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if (IS_SKYLAKE(dev_priv))
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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return skl_decode_mi_display_flip(s, info);
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return skl_decode_mi_display_flip(s, info);
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return -ENODEV;
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return -ENODEV;
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@ -1278,7 +1278,9 @@ static int check_mi_display_flip(struct parser_exec_state *s,
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{
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{
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struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
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struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
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if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
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if (IS_BROADWELL(dev_priv)
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|| IS_SKYLAKE(dev_priv)
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|| IS_KABYLAKE(dev_priv))
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return gen8_check_mi_display_flip(s, info);
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return gen8_check_mi_display_flip(s, info);
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return -ENODEV;
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return -ENODEV;
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}
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}
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@ -1289,7 +1291,9 @@ static int update_plane_mmio_from_mi_display_flip(
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{
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{
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struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
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struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
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if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
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if (IS_BROADWELL(dev_priv)
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|| IS_SKYLAKE(dev_priv)
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|| IS_KABYLAKE(dev_priv))
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return gen8_update_plane_mmio_from_mi_display_flip(s, info);
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return gen8_update_plane_mmio_from_mi_display_flip(s, info);
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return -ENODEV;
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return -ENODEV;
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}
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}
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@ -1569,7 +1573,8 @@ static int batch_buffer_needs_scan(struct parser_exec_state *s)
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{
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{
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struct intel_gvt *gvt = s->vgpu->gvt;
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struct intel_gvt *gvt = s->vgpu->gvt;
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if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {
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if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
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|| IS_KABYLAKE(gvt->dev_priv)) {
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/* BDW decides privilege based on address space */
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/* BDW decides privilege based on address space */
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if (cmd_val(s, 0) & (1 << 8))
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if (cmd_val(s, 0) & (1 << 8))
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return 0;
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return 0;
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@ -173,7 +173,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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SDE_PORTC_HOTPLUG_CPT |
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SDE_PORTC_HOTPLUG_CPT |
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SDE_PORTD_HOTPLUG_CPT);
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SDE_PORTD_HOTPLUG_CPT);
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if (IS_SKYLAKE(dev_priv)) {
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
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vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
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SDE_PORTE_HOTPLUG_SPT);
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SDE_PORTE_HOTPLUG_SPT);
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vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
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vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
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@ -203,7 +203,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
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vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
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}
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}
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if (IS_SKYLAKE(dev_priv) &&
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if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
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intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
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intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
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vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
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vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
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}
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}
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@ -365,7 +365,7 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
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{
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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if (IS_SKYLAKE(dev_priv))
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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clean_virtual_dp_monitor(vgpu, PORT_D);
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clean_virtual_dp_monitor(vgpu, PORT_D);
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else
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else
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clean_virtual_dp_monitor(vgpu, PORT_B);
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clean_virtual_dp_monitor(vgpu, PORT_B);
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@ -387,7 +387,7 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
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intel_vgpu_init_i2c_edid(vgpu);
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intel_vgpu_init_i2c_edid(vgpu);
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if (IS_SKYLAKE(dev_priv))
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
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return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
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resolution);
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resolution);
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else
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else
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@ -2220,7 +2220,8 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
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gvt_dbg_core("init gtt\n");
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gvt_dbg_core("init gtt\n");
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if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {
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if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
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|| IS_KABYLAKE(gvt->dev_priv)) {
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gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
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gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
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gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
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gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
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gvt->gtt.mm_alloc_page_table = gen8_mm_alloc_page_table;
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gvt->gtt.mm_alloc_page_table = gen8_mm_alloc_page_table;
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@ -106,7 +106,8 @@ static void init_device_info(struct intel_gvt *gvt)
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struct intel_gvt_device_info *info = &gvt->device_info;
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struct intel_gvt_device_info *info = &gvt->device_info;
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struct pci_dev *pdev = gvt->dev_priv->drm.pdev;
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struct pci_dev *pdev = gvt->dev_priv->drm.pdev;
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if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {
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if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
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|| IS_KABYLAKE(gvt->dev_priv)) {
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info->max_support_vgpus = 8;
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info->max_support_vgpus = 8;
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info->cfg_space_size = 256;
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info->cfg_space_size = 256;
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info->mmio_size = 2 * 1024 * 1024;
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info->mmio_size = 2 * 1024 * 1024;
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@ -68,6 +68,8 @@ unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
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return D_BDW;
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return D_BDW;
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else if (IS_SKYLAKE(gvt->dev_priv))
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else if (IS_SKYLAKE(gvt->dev_priv))
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return D_SKL;
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return D_SKL;
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else if (IS_KABYLAKE(gvt->dev_priv))
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return D_KBL;
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return 0;
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return 0;
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}
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}
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@ -234,7 +236,8 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu,
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old = vgpu_vreg(vgpu, offset);
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old = vgpu_vreg(vgpu, offset);
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new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
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new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
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if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
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if (IS_SKYLAKE(vgpu->gvt->dev_priv)
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|| IS_KABYLAKE(vgpu->gvt->dev_priv)) {
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switch (offset) {
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switch (offset) {
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case FORCEWAKE_RENDER_GEN9_REG:
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case FORCEWAKE_RENDER_GEN9_REG:
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ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
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ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
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@ -823,8 +826,9 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
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write_vreg(vgpu, offset, p_data, bytes);
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write_vreg(vgpu, offset, p_data, bytes);
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data = vgpu_vreg(vgpu, offset);
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data = vgpu_vreg(vgpu, offset);
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if (IS_SKYLAKE(vgpu->gvt->dev_priv) &&
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if ((IS_SKYLAKE(vgpu->gvt->dev_priv)
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offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
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|| IS_KABYLAKE(vgpu->gvt->dev_priv))
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&& offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
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/* SKL DPB/C/D aux ctl register changed */
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/* SKL DPB/C/D aux ctl register changed */
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return 0;
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return 0;
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} else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
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} else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
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@ -1303,7 +1307,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
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switch (cmd) {
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switch (cmd) {
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case GEN9_PCODE_READ_MEM_LATENCY:
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case GEN9_PCODE_READ_MEM_LATENCY:
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if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
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if (IS_SKYLAKE(vgpu->gvt->dev_priv)
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|| IS_KABYLAKE(vgpu->gvt->dev_priv)) {
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/**
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/**
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* "Read memory latency" command on gen9.
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* "Read memory latency" command on gen9.
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* Below memory latency values are read
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* Below memory latency values are read
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@ -1316,7 +1321,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
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}
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}
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break;
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break;
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case SKL_PCODE_CDCLK_CONTROL:
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case SKL_PCODE_CDCLK_CONTROL:
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if (IS_SKYLAKE(vgpu->gvt->dev_priv))
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if (IS_SKYLAKE(vgpu->gvt->dev_priv)
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|| IS_KABYLAKE(vgpu->gvt->dev_priv))
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*data0 = SKL_CDCLK_READY_FOR_CHANGE;
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*data0 = SKL_CDCLK_READY_FOR_CHANGE;
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break;
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break;
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case GEN6_PCODE_READ_RC6VIDS:
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case GEN6_PCODE_READ_RC6VIDS:
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@ -2886,7 +2892,8 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
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ret = init_broadwell_mmio_info(gvt);
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ret = init_broadwell_mmio_info(gvt);
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if (ret)
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if (ret)
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goto err;
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goto err;
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} else if (IS_SKYLAKE(dev_priv)) {
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} else if (IS_SKYLAKE(dev_priv)
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|| IS_KABYLAKE(dev_priv)) {
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ret = init_broadwell_mmio_info(gvt);
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ret = init_broadwell_mmio_info(gvt);
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if (ret)
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if (ret)
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goto err;
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goto err;
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@ -580,7 +580,7 @@ static void gen8_init_irq(
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SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
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SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
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SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
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SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
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} else if (IS_SKYLAKE(gvt->dev_priv)) {
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} else if (IS_SKYLAKE(gvt->dev_priv) || IS_KABYLAKE(gvt->dev_priv)) {
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SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
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SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
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SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
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SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
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SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
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SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
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@ -690,7 +690,8 @@ int intel_gvt_init_irq(struct intel_gvt *gvt)
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gvt_dbg_core("init irq framework\n");
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gvt_dbg_core("init irq framework\n");
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if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {
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if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
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|| IS_KABYLAKE(gvt->dev_priv)) {
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irq->ops = &gen8_irq_ops;
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irq->ops = &gen8_irq_ops;
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irq->irq_map = gen8_irq_map;
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irq->irq_map = gen8_irq_map;
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} else {
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} else {
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@ -171,7 +171,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
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*/
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*/
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fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
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fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
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FW_REG_READ | FW_REG_WRITE);
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FW_REG_READ | FW_REG_WRITE);
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if (ring_id == RCS && IS_SKYLAKE(dev_priv))
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if (ring_id == RCS && (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
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fw |= FORCEWAKE_RENDER;
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fw |= FORCEWAKE_RENDER;
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intel_uncore_forcewake_get(dev_priv, fw);
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intel_uncore_forcewake_get(dev_priv, fw);
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@ -204,7 +204,7 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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return;
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if (!IS_SKYLAKE(dev_priv))
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if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
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return;
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return;
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offset.reg = regs[ring_id];
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offset.reg = regs[ring_id];
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@ -242,7 +242,7 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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return;
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if (!IS_SKYLAKE(dev_priv))
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if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
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return;
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return;
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offset.reg = regs[ring_id];
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offset.reg = regs[ring_id];
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@ -277,7 +277,8 @@ void intel_gvt_load_render_mmio(struct intel_vgpu *vgpu, int ring_id)
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u32 inhibit_mask =
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u32 inhibit_mask =
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_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
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_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
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if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
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if (IS_SKYLAKE(vgpu->gvt->dev_priv)
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|| IS_KABYLAKE(vgpu->gvt->dev_priv)) {
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mmio = gen9_render_mmio_list;
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mmio = gen9_render_mmio_list;
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array_size = ARRAY_SIZE(gen9_render_mmio_list);
|
array_size = ARRAY_SIZE(gen9_render_mmio_list);
|
||||||
load_mocs(vgpu, ring_id);
|
load_mocs(vgpu, ring_id);
|
||||||
|
@ -324,7 +325,7 @@ void intel_gvt_restore_render_mmio(struct intel_vgpu *vgpu, int ring_id)
|
||||||
u32 v;
|
u32 v;
|
||||||
int i, array_size;
|
int i, array_size;
|
||||||
|
|
||||||
if (IS_SKYLAKE(dev_priv)) {
|
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
||||||
mmio = gen9_render_mmio_list;
|
mmio = gen9_render_mmio_list;
|
||||||
array_size = ARRAY_SIZE(gen9_render_mmio_list);
|
array_size = ARRAY_SIZE(gen9_render_mmio_list);
|
||||||
restore_mocs(vgpu, ring_id);
|
restore_mocs(vgpu, ring_id);
|
||||||
|
|
|
@ -448,7 +448,8 @@ static int workload_thread(void *priv)
|
||||||
struct intel_vgpu_workload *workload = NULL;
|
struct intel_vgpu_workload *workload = NULL;
|
||||||
struct intel_vgpu *vgpu = NULL;
|
struct intel_vgpu *vgpu = NULL;
|
||||||
int ret;
|
int ret;
|
||||||
bool need_force_wake = IS_SKYLAKE(gvt->dev_priv);
|
bool need_force_wake = IS_SKYLAKE(gvt->dev_priv)
|
||||||
|
|| IS_KABYLAKE(gvt->dev_priv);
|
||||||
DEFINE_WAIT_FUNC(wait, woken_wake_function);
|
DEFINE_WAIT_FUNC(wait, woken_wake_function);
|
||||||
|
|
||||||
kfree(p);
|
kfree(p);
|
||||||
|
|
Loading…
Reference in a new issue