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serial: pl011: Drop CR register reset on set_termios
pl011_set_termios() briefly resets the CR register to zero, thereby glitching DTR/RTS signals. With rs485 this may result in the bus being occupied for no reason. Where does this register write originate from? The PL011 driver was forked from the PL010 driver in 2004: https://git.kernel.org/history/history/c/157c0342e591 Until this commit, the PL010 driver's IRQ handler ambauart_int() modified the CR register without holding the port spinlock. ambauart_set_termios() also modified that register. To prevent concurrent read-modify-writes by the IRQ handler and to prevent transmission while changing baudrate, ambauart_set_termios() had to disable interrupts. On the PL010, that is achieved by writing zero to the CR register. However, on the PL011, interrupts are disabled in the IMSC register, not in the CR register. Additionally, the commit amended both the PL010 and PL011 driver to acquire the port spinlock in the IRQ handler, obviating the need to disable interrupts in ->set_termios(). So the CR register write is obsolete for two reasons. Drop it. Cc: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Lukas Wunner <lukas@wunner.de> Link: https://lore.kernel.org/r/f49f945375f5ccb979893c49f1129f51651ac738.1641129062.git.lukas@wunner.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -2073,9 +2073,7 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
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if (port->rs485.flags & SER_RS485_ENABLED)
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termios->c_cflag &= ~CRTSCTS;
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/* first, disable everything */
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old_cr = pl011_read(uap, REG_CR);
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pl011_write(0, uap, REG_CR);
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if (termios->c_cflag & CRTSCTS) {
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if (old_cr & UART011_CR_RTS)
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