mmc: dw_mmc: add support for hi3798cv200 specific extensions of dw-mshc
Hi3798CV200 SoC extends the dw-mshc controller for additional clock and bus control. Add support for these extensions. Signed-off-by: tianshuliang <tianshuliang@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
tianshuliang
Ulf Hansson
parent
8a9cdf9852
commit
e382ab7412
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@ -718,6 +718,15 @@ config MMC_DW_EXYNOS
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Synopsys DesignWare Memory Card Interface driver. Select this option
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for platforms based on Exynos4 and Exynos5 SoC's.
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config MMC_DW_HI3798CV200
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tristate "Hi3798CV200 specific extensions for Synopsys DW Memory Card Interface"
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depends on MMC_DW
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select MMC_DW_PLTFM
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help
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This selects support for HiSilicon Hi3798CV200 SoC specific extensions to the
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Synopsys DesignWare Memory Card Interface driver. Select this option
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for platforms based on HiSilicon Hi3798CV200 SoC.
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config MMC_DW_K3
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tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
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depends on MMC_DW
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@ -51,6 +51,7 @@ obj-$(CONFIG_MMC_CAVIUM_THUNDERX) += thunderx-mmc.o
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obj-$(CONFIG_MMC_DW) += dw_mmc.o
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obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o
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obj-$(CONFIG_MMC_DW_EXYNOS) += dw_mmc-exynos.o
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obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o
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obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
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obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
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obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
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@ -0,0 +1,202 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mmc/host.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define ALL_INT_CLR 0x1ffff
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struct hi3798cv200_priv {
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struct clk *sample_clk;
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struct clk *drive_clk;
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};
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static void dw_mci_hi3798cv200_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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struct hi3798cv200_priv *priv = host->priv;
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u32 val;
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val = mci_readl(host, UHS_REG);
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if (ios->timing == MMC_TIMING_MMC_DDR52 ||
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ios->timing == MMC_TIMING_UHS_DDR50)
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val |= SDMMC_UHS_DDR;
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else
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val &= ~SDMMC_UHS_DDR;
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mci_writel(host, UHS_REG, val);
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val = mci_readl(host, ENABLE_SHIFT);
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if (ios->timing == MMC_TIMING_MMC_DDR52)
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val |= SDMMC_ENABLE_PHASE;
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else
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val &= ~SDMMC_ENABLE_PHASE;
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mci_writel(host, ENABLE_SHIFT, val);
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val = mci_readl(host, DDR_REG);
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if (ios->timing == MMC_TIMING_MMC_HS400)
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val |= SDMMC_DDR_HS400;
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else
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val &= ~SDMMC_DDR_HS400;
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mci_writel(host, DDR_REG, val);
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if (ios->timing == MMC_TIMING_MMC_HS ||
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ios->timing == MMC_TIMING_LEGACY)
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clk_set_phase(priv->drive_clk, 180);
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else if (ios->timing == MMC_TIMING_MMC_HS200)
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clk_set_phase(priv->drive_clk, 135);
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}
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static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot,
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u32 opcode)
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{
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int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 };
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struct dw_mci *host = slot->host;
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struct hi3798cv200_priv *priv = host->priv;
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int raise_point = -1, fall_point = -1;
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int err, prev_err = -1;
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int found = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(degrees); i++) {
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clk_set_phase(priv->sample_clk, degrees[i]);
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mci_writel(host, RINTSTS, ALL_INT_CLR);
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err = mmc_send_tuning(slot->mmc, opcode, NULL);
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if (!err)
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found = 1;
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if (i > 0) {
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if (err && !prev_err)
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fall_point = i - 1;
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if (!err && prev_err)
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raise_point = i;
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}
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if (raise_point != -1 && fall_point != -1)
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goto tuning_out;
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prev_err = err;
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err = 0;
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}
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tuning_out:
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if (found) {
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if (raise_point == -1)
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raise_point = 0;
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if (fall_point == -1)
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fall_point = ARRAY_SIZE(degrees) - 1;
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if (fall_point < raise_point) {
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if ((raise_point + fall_point) >
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(ARRAY_SIZE(degrees) - 1))
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i = fall_point / 2;
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else
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i = (raise_point + ARRAY_SIZE(degrees) - 1) / 2;
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} else {
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i = (raise_point + fall_point) / 2;
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}
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clk_set_phase(priv->sample_clk, degrees[i]);
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dev_dbg(host->dev, "Tuning clk_sample[%d, %d], set[%d]\n",
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raise_point, fall_point, degrees[i]);
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} else {
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dev_err(host->dev, "No valid clk_sample shift! use default\n");
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err = -EINVAL;
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}
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mci_writel(host, RINTSTS, ALL_INT_CLR);
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return err;
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}
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static int dw_mci_hi3798cv200_init(struct dw_mci *host)
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{
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struct hi3798cv200_priv *priv;
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int ret;
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priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
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if (IS_ERR(priv->sample_clk)) {
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dev_err(host->dev, "failed to get ciu-sample clock\n");
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return PTR_ERR(priv->sample_clk);
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}
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priv->drive_clk = devm_clk_get(host->dev, "ciu-drive");
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if (IS_ERR(priv->drive_clk)) {
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dev_err(host->dev, "failed to get ciu-drive clock\n");
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return PTR_ERR(priv->drive_clk);
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}
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ret = clk_prepare_enable(priv->sample_clk);
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if (ret) {
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dev_err(host->dev, "failed to enable ciu-sample clock\n");
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return ret;
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}
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ret = clk_prepare_enable(priv->drive_clk);
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if (ret) {
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dev_err(host->dev, "failed to enable ciu-drive clock\n");
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goto disable_sample_clk;
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}
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host->priv = priv;
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return 0;
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disable_sample_clk:
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clk_disable_unprepare(priv->sample_clk);
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return ret;
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}
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static const struct dw_mci_drv_data hi3798cv200_data = {
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.init = dw_mci_hi3798cv200_init,
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.set_ios = dw_mci_hi3798cv200_set_ios,
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.execute_tuning = dw_mci_hi3798cv200_execute_tuning,
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};
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static int dw_mci_hi3798cv200_probe(struct platform_device *pdev)
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{
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return dw_mci_pltfm_register(pdev, &hi3798cv200_data);
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}
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static int dw_mci_hi3798cv200_remove(struct platform_device *pdev)
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{
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struct dw_mci *host = platform_get_drvdata(pdev);
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struct hi3798cv200_priv *priv = host->priv;
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clk_disable_unprepare(priv->drive_clk);
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clk_disable_unprepare(priv->sample_clk);
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return dw_mci_pltfm_remove(pdev);
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}
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static const struct of_device_id dw_mci_hi3798cv200_match[] = {
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{ .compatible = "hisilicon,hi3798cv200-dw-mshc", },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_mci_hi3798cv200_match);
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static struct platform_driver dw_mci_hi3798cv200_driver = {
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.probe = dw_mci_hi3798cv200_probe,
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.remove = dw_mci_hi3798cv200_remove,
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.driver = {
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.name = "dwmmc_hi3798cv200",
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.of_match_table = dw_mci_hi3798cv200_match,
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},
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};
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module_platform_driver(dw_mci_hi3798cv200_driver);
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MODULE_DESCRIPTION("HiSilicon Hi3798CV200 Specific DW-MSHC Driver Extension");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:dwmmc_hi3798cv200");
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@ -314,6 +314,7 @@ struct dw_mci_board {
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#define SDMMC_BUFADDR 0x098
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#define SDMMC_CDTHRCTL 0x100
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#define SDMMC_UHS_REG_EXT 0x108
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#define SDMMC_DDR_REG 0x10c
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#define SDMMC_ENABLE_SHIFT 0x110
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#define SDMMC_DATA(x) (x)
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/*
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@ -439,7 +440,12 @@ struct dw_mci_board {
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#define SDMMC_CARD_WR_THR_EN BIT(2)
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#define SDMMC_CARD_RD_THR_EN BIT(0)
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/* UHS-1 register defines */
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#define SDMMC_UHS_DDR BIT(16)
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#define SDMMC_UHS_18V BIT(0)
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/* DDR register defines */
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#define SDMMC_DDR_HS400 BIT(31)
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/* Enable shift register defines */
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#define SDMMC_ENABLE_PHASE BIT(0)
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/* All ctrl reset bits */
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#define SDMMC_CTRL_ALL_RESET_FLAGS \
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(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
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