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drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs
when cat pp_od_clk_voltage it show OD_SCLK: 0: 300Mhz 800 mV 1: 466Mhz 818 mV 2: 751Mhz 824 mV 3: 1019Mhz 987 mV 4: 1074Mhz 1037 mV 5: 1126Mhz 1087 mV 6: 1169Mhz 1137 mV 7: 1206Mhz 1150 mV OD_MCLK: 0: 300Mhz 800 mV 1: 1650Mhz 1000 mV echo "s/m level clock voltage" to change sclk/mclk's clock and voltage echo "r" to restore default value. echo "c" to commit the user setting. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
897e1bbeec
commit
e3933f26b6
4 changed files with 121 additions and 1 deletions
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@ -374,6 +374,10 @@ enum amdgpu_pcie_gen {
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((adev)->powerplay.pp_funcs->set_power_profile_mode(\
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(adev)->powerplay.pp_handle, parameter, size))
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#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
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((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
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(adev)->powerplay.pp_handle, type, parameter, size))
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struct amdgpu_dpm {
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struct amdgpu_ps *ps;
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/* number of valid power states */
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@ -360,6 +360,90 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
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return count;
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}
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static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t count)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = ddev->dev_private;
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int ret;
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uint32_t parameter_size = 0;
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long parameter[64];
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char buf_cpy[128];
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char *tmp_str;
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char *sub_str;
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const char delimiter[3] = {' ', '\n', '\0'};
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uint32_t type;
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if (count > 127)
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return -EINVAL;
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if (*buf == 's')
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type = PP_OD_EDIT_SCLK_VDDC_TABLE;
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else if (*buf == 'm')
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type = PP_OD_EDIT_MCLK_VDDC_TABLE;
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else if(*buf == 'r')
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type = PP_OD_RESTORE_DEFAULT_TABLE;
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else if (*buf == 'c')
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type = PP_OD_COMMIT_DPM_TABLE;
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else
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return -EINVAL;
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memcpy(buf_cpy, buf, count+1);
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tmp_str = buf_cpy;
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while (isspace(*++tmp_str));
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while (tmp_str[0]) {
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sub_str = strsep(&tmp_str, delimiter);
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ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
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if (ret)
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return -EINVAL;
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parameter_size++;
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while (isspace(*tmp_str))
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tmp_str++;
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}
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if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
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ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
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parameter, parameter_size);
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if (ret)
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return -EINVAL;
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if (type == PP_OD_COMMIT_DPM_TABLE) {
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if (adev->powerplay.pp_funcs->dispatch_tasks) {
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amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
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return count;
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} else {
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return -EINVAL;
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}
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}
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return count;
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}
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static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = ddev->dev_private;
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uint32_t size = 0;
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if (adev->powerplay.pp_funcs->print_clock_levels) {
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size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
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size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
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return size;
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} else {
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return snprintf(buf, PAGE_SIZE, "\n");
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}
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}
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static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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@ -842,6 +926,10 @@ static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
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static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
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amdgpu_get_pp_power_profile_mode,
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amdgpu_set_pp_power_profile_mode);
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static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
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amdgpu_get_pp_od_clk_voltage,
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amdgpu_set_pp_od_clk_voltage);
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static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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@ -1481,7 +1569,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
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"pp_power_profile_mode\n");
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return ret;
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}
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ret = device_create_file(adev->dev,
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&dev_attr_pp_od_clk_voltage);
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if (ret) {
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DRM_ERROR("failed to create device file "
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"pp_od_clk_voltage\n");
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return ret;
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}
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ret = amdgpu_debugfs_pm_init(adev);
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if (ret) {
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DRM_ERROR("Failed to register debugfs file for dpm!\n");
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@ -1519,6 +1613,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
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&dev_attr_pp_compute_power_profile);
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device_remove_file(adev->dev,
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&dev_attr_pp_power_profile_mode);
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device_remove_file(adev->dev,
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&dev_attr_pp_od_clk_voltage);
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}
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void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
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@ -310,6 +310,7 @@ struct amd_pm_funcs {
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struct amd_pp_simple_clock_info *clocks);
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int (*get_power_profile_mode)(void *handle, char *buf);
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int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
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int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
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};
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#endif
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@ -1122,6 +1122,24 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
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return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
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}
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static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
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{
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struct pp_hwmgr *hwmgr;
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struct pp_instance *pp_handle = (struct pp_instance *)handle;
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if (pp_check(pp_handle))
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return -EINVAL;
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hwmgr = pp_handle->hwmgr;
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if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
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pr_info("%s was not implemented.\n", __func__);
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return -EINVAL;
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}
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return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
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}
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static int pp_dpm_set_power_profile_state(void *handle,
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struct amd_pp_profile *request)
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{
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@ -1507,6 +1525,7 @@ const struct amd_pm_funcs pp_dpm_funcs = {
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.notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
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.get_power_profile_mode = pp_get_power_profile_mode,
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.set_power_profile_mode = pp_set_power_profile_mode,
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.odn_edit_dpm_table = pp_odn_edit_dpm_table,
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/* export to DC */
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.get_sclk = pp_dpm_get_sclk,
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.get_mclk = pp_dpm_get_mclk,
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