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thermal: exynos: remove parsing of samsung, tmu[_min, _max]_efuse_value properties
Since pdata efuse values are SoC (not platform) specific just move them from platform data to struct exynos_tmu_data instance. Then remove parsing of samsung,tmu[_,min_,max]_efuse_value properties. There should be no functional changes caused by this patch. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
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09d29426bc
commit
e3ed36499b
2 changed files with 32 additions and 24 deletions
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@ -185,6 +185,9 @@
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* @clk: pointer to the clock structure.
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* @clk_sec: pointer to the clock structure for accessing the base_second.
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* @sclk: pointer to the clock structure for accessing the tmu special clk.
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* @efuse_value: SoC defined fuse value
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* @min_efuse_value: minimum valid trimming data
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* @max_efuse_value: maximum valid trimming data
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* @temp_error1: fused value of the first point trim.
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* @temp_error2: fused value of the second point trim.
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* @regulator: pointer to the TMU regulator structure.
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@ -207,6 +210,9 @@ struct exynos_tmu_data {
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struct work_struct irq_work;
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struct mutex lock;
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struct clk *clk, *clk_sec, *sclk;
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u32 efuse_value;
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u32 min_efuse_value;
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u32 max_efuse_value;
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u16 temp_error1, temp_error2;
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struct regulator *regulator;
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struct thermal_zone_device *tzd;
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@ -283,20 +289,18 @@ static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
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static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
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{
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struct exynos_tmu_platform_data *pdata = data->pdata;
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data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
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data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
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EXYNOS_TMU_TEMP_MASK);
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if (!data->temp_error1 ||
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(pdata->min_efuse_value > data->temp_error1) ||
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(data->temp_error1 > pdata->max_efuse_value))
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data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
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(data->min_efuse_value > data->temp_error1) ||
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(data->temp_error1 > data->max_efuse_value))
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data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK;
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if (!data->temp_error2)
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data->temp_error2 =
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(pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
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(data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
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EXYNOS_TMU_TEMP_MASK;
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}
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@ -655,7 +659,6 @@ static int exynos7_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct thermal_zone_device *tz = data->tzd;
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struct exynos_tmu_platform_data *pdata = data->pdata;
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unsigned int status, trim_info;
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unsigned int rising_threshold = 0, falling_threshold = 0;
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int ret = 0, threshold_code, i;
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@ -672,9 +675,9 @@ static int exynos7_tmu_initialize(struct platform_device *pdev)
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data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK;
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if (!data->temp_error1 ||
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(pdata->min_efuse_value > data->temp_error1) ||
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(data->temp_error1 > pdata->max_efuse_value))
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data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
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(data->min_efuse_value > data->temp_error1) ||
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(data->temp_error1 > data->max_efuse_value))
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data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK;
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/* Write temperature code for rising and falling threshold */
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for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) {
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@ -1136,13 +1139,6 @@ static int exynos_of_sensor_conf(struct device_node *np,
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of_property_read_u32(np, "samsung,tmu_reference_voltage", &value);
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pdata->reference_voltage = (u8)value;
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of_property_read_u32(np, "samsung,tmu_efuse_value",
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&pdata->efuse_value);
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of_property_read_u32(np, "samsung,tmu_min_efuse_value",
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&pdata->min_efuse_value);
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of_property_read_u32(np, "samsung,tmu_max_efuse_value",
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&pdata->max_efuse_value);
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of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type);
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of_node_put(np);
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@ -1196,6 +1192,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
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data->tmu_read = exynos4210_tmu_read;
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data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
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data->ntrip = 4;
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data->efuse_value = 55;
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data->min_efuse_value = 40;
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data->max_efuse_value = 100;
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break;
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case SOC_ARCH_EXYNOS3250:
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case SOC_ARCH_EXYNOS4412:
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@ -1209,6 +1208,13 @@ static int exynos_map_dt_data(struct platform_device *pdev)
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data->tmu_set_emulation = exynos4412_tmu_set_emulation;
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data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
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data->ntrip = 4;
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data->efuse_value = 55;
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if (data->soc != SOC_ARCH_EXYNOS5420 &&
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data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)
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data->min_efuse_value = 40;
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else
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data->min_efuse_value = 0;
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data->max_efuse_value = 100;
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break;
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case SOC_ARCH_EXYNOS5433:
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data->tmu_initialize = exynos5433_tmu_initialize;
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@ -1217,6 +1223,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
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data->tmu_set_emulation = exynos4412_tmu_set_emulation;
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data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
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data->ntrip = 8;
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data->efuse_value = 75;
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data->min_efuse_value = 40;
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data->max_efuse_value = 150;
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break;
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case SOC_ARCH_EXYNOS5440:
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data->tmu_initialize = exynos5440_tmu_initialize;
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@ -1225,6 +1234,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
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data->tmu_set_emulation = exynos5440_tmu_set_emulation;
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data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
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data->ntrip = 4;
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data->efuse_value = 0x5d2d;
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data->min_efuse_value = 16;
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data->max_efuse_value = 76;
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break;
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case SOC_ARCH_EXYNOS7:
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data->tmu_initialize = exynos7_tmu_initialize;
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@ -1233,6 +1245,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
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data->tmu_set_emulation = exynos4412_tmu_set_emulation;
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data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
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data->ntrip = 8;
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data->efuse_value = 75;
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data->min_efuse_value = 15;
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data->max_efuse_value = 100;
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break;
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default:
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dev_err(&pdev->dev, "Platform not supported\n");
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@ -45,9 +45,6 @@ enum soc_type {
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* @reference_voltage: reference voltage of amplifier
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* in the positive-TC generator block
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* 0 < reference_voltage <= 31
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* @efuse_value: platform defined fuse value
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* @min_efuse_value: minimum valid trimming data
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* @max_efuse_value: maximum valid trimming data
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* @cal_type: calibration type for temperature
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*
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* This structure is required for configuration of exynos_tmu driver.
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@ -56,10 +53,6 @@ struct exynos_tmu_platform_data {
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u8 gain;
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u8 reference_voltage;
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u32 efuse_value;
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u32 min_efuse_value;
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u32 max_efuse_value;
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u32 cal_type;
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};
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