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dt-bindings: net: can: add STM32 bxcan DT bindings
Add documentation of device tree bindings for the STM32 basic extended CAN (bxcan) controller. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/all/20230328073328.3949796-3-dario.binacchi@amarulasolutions.com [mkl: drop unneeded quotes] Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics bxCAN controller
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description: STMicroelectronics BxCAN controller for CAN bus
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maintainers:
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- Dario Binacchi <dario.binacchi@amarulasolutions.com>
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allOf:
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- $ref: can-controller.yaml#
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properties:
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compatible:
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enum:
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- st,stm32f4-bxcan
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st,can-primary:
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description:
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Primary and secondary mode of the bxCAN peripheral is only relevant
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if the chip has two CAN peripherals. In that case they share some
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of the required logic.
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To avoid misunderstandings, it should be noted that ST documentation
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uses the terms master/slave instead of primary/secondary.
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type: boolean
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: transmit interrupt
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- description: FIFO 0 receive interrupt
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- description: FIFO 1 receive interrupt
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- description: status change error interrupt
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interrupt-names:
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items:
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- const: tx
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- const: rx0
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- const: rx1
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- const: sce
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resets:
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maxItems: 1
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clocks:
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maxItems: 1
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st,gcan:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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The phandle to the gcan node which allows to access the 512-bytes
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SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2
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secondary) in dual CAN peripheral configuration.
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required:
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- compatible
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- reg
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- interrupts
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- resets
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- clocks
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- st,gcan
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/stm32fx-clock.h>
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#include <dt-bindings/mfd/stm32f4-rcc.h>
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can1: can@40006400 {
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compatible = "st,stm32f4-bxcan";
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reg = <0x40006400 0x200>;
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interrupts = <19>, <20>, <21>, <22>;
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interrupt-names = "tx", "rx0", "rx1", "sce";
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resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
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st,can-primary;
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st,gcan = <&gcan>;
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};
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