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clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro
Convert the boilerplate code for manual addition of the watchdog clock to the new SGRF_GATE macro for all affected socs. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
parent
b3b723d8c4
commit
e4488e45e2
4 changed files with 12 additions and 36 deletions
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@ -803,6 +803,9 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
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GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),
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GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),
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/* aclk_dmac is controlled by sgrf_soc_con1[11]. */
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SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"),
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GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),
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GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),
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GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS),
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@ -966,7 +969,6 @@ static void __init px30_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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struct clk *clk;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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@ -981,14 +983,6 @@ static void __init px30_clk_init(struct device_node *np)
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return;
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}
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/* aclk_dmac is controlled by sgrf_soc_con1[11]. */
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clk = clk_register_fixed_factor(NULL, "aclk_dmac", "aclk_bus_pre", 0, 1, 1);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock aclk_dmac: %ld\n",
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__func__, PTR_ERR(clk));
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else
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rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC);
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rockchip_clk_register_plls(ctx, px30_pll_clks,
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ARRAY_SIZE(px30_pll_clks),
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PX30_GRF_SOC_STATUS0);
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@ -775,6 +775,9 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
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GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
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/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
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SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
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/* pclk_pd_pmu gates */
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GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
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GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
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@ -923,7 +926,6 @@ static struct syscore_ops rk3288_clk_syscore_ops = {
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static void __init rk3288_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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struct clk *clk;
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rk3288_cru_base = of_iomap(np, 0);
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if (!rk3288_cru_base) {
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@ -938,14 +940,6 @@ static void __init rk3288_clk_init(struct device_node *np)
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return;
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}
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/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
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clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock pclk_wdt: %ld\n",
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__func__, PTR_ERR(clk));
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else
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rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
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rockchip_clk_register_plls(ctx, rk3288_pll_clks,
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ARRAY_SIZE(rk3288_pll_clks),
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RK3288_GRF_SOC_STATUS1);
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@ -820,6 +820,9 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
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GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
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/* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
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SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
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/*
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* pclk_vio gates
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* pclk_vio comes from the exactly same source as hclk_vio
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@ -871,7 +874,6 @@ static void __init rk3368_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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struct clk *clk;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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@ -886,14 +888,6 @@ static void __init rk3368_clk_init(struct device_node *np)
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return;
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}
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/* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
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clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock pclk_wdt: %ld\n",
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__func__, PTR_ERR(clk));
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else
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rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
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rockchip_clk_register_plls(ctx, rk3368_pll_clks,
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ARRAY_SIZE(rk3368_pll_clks),
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RK3368_GRF_SOC_STATUS0);
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@ -1304,6 +1304,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
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GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
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/* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
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SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"),
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GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
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GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
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@ -1531,7 +1534,6 @@ static void __init rk3399_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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struct clk *clk;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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@ -1546,14 +1548,6 @@ static void __init rk3399_clk_init(struct device_node *np)
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return;
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}
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/* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
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clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock pclk_wdt: %ld\n",
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__func__, PTR_ERR(clk));
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else
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rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
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rockchip_clk_register_plls(ctx, rk3399_pll_clks,
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ARRAY_SIZE(rk3399_pll_clks), -1);
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