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ARM: pxa: fixes for v4.3
These fixes are mainly regression fixes triggered by irq changes, common clock framework introduction and sound side-effect of other platforms. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV/nW0AAoJEAP2et0duMsSAP0QAKqFrk4GyRNTFxDQNBj43jrS 3dHtbbTp04sf/RotcGbPPfGvWkv4LAc4CGYnMC3lXZw64HdIHtuHiiwrj3eeuoH9 zw0xJpbzcHyu25i9wrOY06WgJ4TfTwqfBhhZZ9xoYs8XjuhbKxOP/X7ytSQ56aK9 iyYCiE4sB4Ikgiu9iOvoztqo3SgtLuK7HYIgV5XASbVqtco4pLfq0upTbfkOesqw V9/+rnG5IaHAxgxuCT/UFg4uP1mW0W8EgC4UGi+Vi2MPQ5kmUwSSTmCcIYGryBem etJth5b8Q0AEnlEnx5plAhCPskpU7YkPCticQAmQkdU3fJC09+rzkgV66dOi64Mz f6YfGH/UXaHZjYZqIDRStN+Bp7HKJRBXNTtRUFfRFY40mKQFrcyrxPmYWIAiwY+E 62O2/qzMMuycxlQo7xhH00qEK9oB2VfshhqXKRHWDhKyAjPbvhF6h0tnHBJSsPzi HJRtzs5dHtCqYBjVY21U391D7IA5lEck4cOExvVRbe1dn2eGbOZcLTS+caZbzhEy ulYbS4QZvtFTh7+dRhpG0jTuxIjMbZskogvOSET/wNuZewu7IrFMZt8ySPFbHwDs h5i+TZVfxcXu8kv+C5rT5q0bAP18p8dzowgzODh5iQpwTLahZ7tUPJmF+sC3QuSd zAOeAqKy3RQ8NL74LMPo =fNDY -----END PGP SIGNATURE----- Merge tag 'pxa-fixes-v4.3' of https://github.com/rjarzmik/linux into fixes ARM: pxa: fixes for v4.3 These fixes are mainly regression fixes triggered by irq changes, common clock framework introduction and sound side-effect of other platforms. * tag 'pxa-fixes-v4.3' of https://github.com/rjarzmik/linux: ARM: pxa: balloon3: Fix build error ARM: pxa: ssp: Fix build error by removing originally incorrect DT binding ARM: pxa: fix DFI bus lockups on startup Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
e46fc90ec2
4 changed files with 28 additions and 3 deletions
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@ -502,7 +502,7 @@ static void balloon3_irq_handler(unsigned int __irq, struct irq_desc *desc)
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balloon3_irq_enabled;
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do {
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struct irq_data *d = irq_desc_get_irq_data(desc);
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struct irq_chip *chip = irq_data_get_chip(d);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int irq;
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/* clear useless edge notification */
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@ -43,6 +43,13 @@
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* 0xf6200000..0xf6201000
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*/
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/*
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* DFI Bus for NAND, PXA3xx only
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*/
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#define NAND_PHYS 0x43100000
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#define NAND_VIRT IOMEM(0xf6300000)
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#define NAND_SIZE 0x00100000
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/*
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* Internal Memory Controller (PXA27x and later)
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*/
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@ -47,6 +47,13 @@ extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
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#define ISRAM_START 0x5c000000
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#define ISRAM_SIZE SZ_256K
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/*
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* NAND NFC: DFI bus arbitration subset
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*/
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#define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0))
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#define NDCR_ND_ARB_EN (1 << 12)
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#define NDCR_ND_ARB_CNTL (1 << 19)
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static void __iomem *sram;
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static unsigned long wakeup_src;
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@ -362,7 +369,12 @@ static struct map_desc pxa3xx_io_desc[] __initdata = {
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.pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
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.length = SMEMC_SIZE,
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.type = MT_DEVICE
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}
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}, {
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.virtual = (unsigned long)NAND_VIRT,
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.pfn = __phys_to_pfn(NAND_PHYS),
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.length = NAND_SIZE,
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.type = MT_DEVICE
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},
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};
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void __init pxa3xx_map_io(void)
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@ -419,6 +431,13 @@ static int __init pxa3xx_init(void)
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*/
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ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
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/*
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* Disable DFI bus arbitration, to prevent a system bus lock if
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* somebody disables the NAND clock (unused clock) while this
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* bit remains set.
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*/
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NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;
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if ((ret = pxa_init_dma(IRQ_DMA, 32)))
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return ret;
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@ -107,7 +107,6 @@ static const struct of_device_id pxa_ssp_of_ids[] = {
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{ .compatible = "mvrl,pxa168-ssp", .data = (void *) PXA168_SSP },
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{ .compatible = "mrvl,pxa910-ssp", .data = (void *) PXA910_SSP },
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{ .compatible = "mrvl,ce4100-ssp", .data = (void *) CE4100_SSP },
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{ .compatible = "mrvl,lpss-ssp", .data = (void *) LPSS_SSP },
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{ },
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};
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MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
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