mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-09-13 14:14:37 +00:00
Code Issues Releases Wiki Activity

scsi: hisi_sas: Ignore the error code between phy down to phy up

Browse source 
Several error codes will be generated between PHY down to up.

This issue was introduced by HW design. The designers came to the
conclusion that we should ignore these errors.

Signed-off-by: Jiaxing Luo <luojiaxing@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Luo Jiaxing 2019-05-29 17:58:46 +08:00 committed by Martin K. Petersen
parent 0ab7bc825a
commit e4c19deba6
1 changed files with 15 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
View file

@ -911,8 +911,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
BIT(CHL_INT2_RX_CODE_ERR_OFF) |
BIT(CHL_INT2_RX_INVLD_DW_OFF);
u32 state;
hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
cfg &= ~PHY_CFG_ENA_MSK;
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
@ -923,6 +929,15 @@ static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
cfg |= PHY_CFG_PHY_RST_MSK;
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
}
udelay(1);
hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
}
static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)