mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-29 13:53:33 +00:00
clk: meson: regmap: switch to determine_rate for the dividers
This increases the maxmium supported frequency on 32-bit systems from 2^31 (signed long as used by clk_ops.round_rate, maximum value: approx. 2.14GHz) to 2^32 (unsigned long as used by clk_ops.determine_rate, maximum value: approx. 4.29GHz). On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are capable of running at up to 2.97GHz. So switch the divider implementation in clk-regmap to clk_ops.determine_rate to support these higher frequencies on 32-bit systems. Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20210627223959.188139-4-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
db400ac144
commit
e4c5ef6b95
1 changed files with 9 additions and 10 deletions
|
@ -75,8 +75,8 @@ static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
|
||||||
div->width);
|
div->width);
|
||||||
}
|
}
|
||||||
|
|
||||||
static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
|
static int clk_regmap_div_determine_rate(struct clk_hw *hw,
|
||||||
unsigned long *prate)
|
struct clk_rate_request *req)
|
||||||
{
|
{
|
||||||
struct clk_regmap *clk = to_clk_regmap(hw);
|
struct clk_regmap *clk = to_clk_regmap(hw);
|
||||||
struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
|
struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
|
||||||
|
@ -87,18 +87,17 @@ static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||||
if (div->flags & CLK_DIVIDER_READ_ONLY) {
|
if (div->flags & CLK_DIVIDER_READ_ONLY) {
|
||||||
ret = regmap_read(clk->map, div->offset, &val);
|
ret = regmap_read(clk->map, div->offset, &val);
|
||||||
if (ret)
|
if (ret)
|
||||||
/* Gives a hint that something is wrong */
|
return ret;
|
||||||
return 0;
|
|
||||||
|
|
||||||
val >>= div->shift;
|
val >>= div->shift;
|
||||||
val &= clk_div_mask(div->width);
|
val &= clk_div_mask(div->width);
|
||||||
|
|
||||||
return divider_ro_round_rate(hw, rate, prate, div->table,
|
return divider_ro_determine_rate(hw, req, div->table,
|
||||||
div->width, div->flags, val);
|
div->width, div->flags, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
return divider_round_rate(hw, rate, prate, div->table, div->width,
|
return divider_determine_rate(hw, req, div->table, div->width,
|
||||||
div->flags);
|
div->flags);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||||
|
@ -123,14 +122,14 @@ static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||||
|
|
||||||
const struct clk_ops clk_regmap_divider_ops = {
|
const struct clk_ops clk_regmap_divider_ops = {
|
||||||
.recalc_rate = clk_regmap_div_recalc_rate,
|
.recalc_rate = clk_regmap_div_recalc_rate,
|
||||||
.round_rate = clk_regmap_div_round_rate,
|
.determine_rate = clk_regmap_div_determine_rate,
|
||||||
.set_rate = clk_regmap_div_set_rate,
|
.set_rate = clk_regmap_div_set_rate,
|
||||||
};
|
};
|
||||||
EXPORT_SYMBOL_GPL(clk_regmap_divider_ops);
|
EXPORT_SYMBOL_GPL(clk_regmap_divider_ops);
|
||||||
|
|
||||||
const struct clk_ops clk_regmap_divider_ro_ops = {
|
const struct clk_ops clk_regmap_divider_ro_ops = {
|
||||||
.recalc_rate = clk_regmap_div_recalc_rate,
|
.recalc_rate = clk_regmap_div_recalc_rate,
|
||||||
.round_rate = clk_regmap_div_round_rate,
|
.determine_rate = clk_regmap_div_determine_rate,
|
||||||
};
|
};
|
||||||
EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops);
|
EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops);
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue