From e4cd854ec487fde631fe57049f588d2396da281c Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 19 Apr 2021 00:19:46 +0200 Subject: [PATCH] net: korina: Get mdio input clock via common clock framework With device tree clock is provided via CCF. For non device tree use a maximum clock value to not overclock the PHY. The non device tree usage will go away after platform is converted to DT. Signed-off-by: Thomas Bogendoerfer Signed-off-by: David S. Miller --- drivers/net/ethernet/korina.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/korina.c b/drivers/net/ethernet/korina.c index a1f53d7753ae..19f226428f89 100644 --- a/drivers/net/ethernet/korina.c +++ b/drivers/net/ethernet/korina.c @@ -57,14 +57,13 @@ #include #include #include +#include #include #include #include #include -#include -#include #include #include @@ -146,10 +145,9 @@ struct korina_private { struct work_struct restart_task; struct net_device *dev; struct device *dmadev; + int mii_clock_freq; }; -extern unsigned int idt_cpu_freq; - static dma_addr_t korina_tx_dma(struct korina_private *lp, int idx) { return lp->td_dma + (idx * sizeof(struct dma_desc)); @@ -899,8 +897,8 @@ static int korina_init(struct net_device *dev) /* Management Clock Prescaler Divisor * Clock independent setting */ - writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1, - &lp->eth_regs->ethmcp); + writel(((lp->mii_clock_freq) / MII_CLOCK + 1) & ~1, + &lp->eth_regs->ethmcp); writel(0, &lp->eth_regs->miimcfg); /* don't transmit until fifo contains 48b */ @@ -1060,6 +1058,7 @@ static int korina_probe(struct platform_device *pdev) u8 *mac_addr = dev_get_platdata(&pdev->dev); struct korina_private *lp; struct net_device *dev; + struct clk *clk; void __iomem *p; int rc; @@ -1075,6 +1074,16 @@ static int korina_probe(struct platform_device *pdev) else if (of_get_mac_address(pdev->dev.of_node, dev->dev_addr) < 0) eth_hw_addr_random(dev); + clk = devm_clk_get_optional(&pdev->dev, "mdioclk"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + if (clk) { + clk_prepare_enable(clk); + lp->mii_clock_freq = clk_get_rate(clk); + } else { + lp->mii_clock_freq = 200000000; /* max possible input clk */ + } + lp->rx_irq = platform_get_irq_byname(pdev, "rx"); lp->tx_irq = platform_get_irq_byname(pdev, "tx");