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Merge branch 'mellanox/mlx5-next' into rdma.git for/next

Browse source 
From the mlx5-next branch at
  git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

Required for dependencies in following patches

* branch 'mellanox/mlx5-next':
  net/mlx5: Add ability to read and write ECE options
  net/mlx5: Add support for RDMA TX FT headers modifying
  net/mlx5: Move iseg access helper routines close to mlx5_core driver
  net/mlx5: Cleanup mlx5_ifc_fte_match_set_misc2_bits

Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Jason Gunthorpe 2020-05-27 16:01:17 -03:00
commit e4fdf7625b
8 changed files with 36 additions and 27 deletions
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5
drivers/infiniband/hw/mlx5/flow.c
View file

@ -438,7 +438,10 @@ static bool mlx5_ib_modify_header_supported(struct mlx5_ib_dev *dev)
{ {
return MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, return MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
max_modify_header_actions) || max_modify_header_actions) ||
MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, max_modify_header_actions); MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
max_modify_header_actions) ||
MLX5_CAP_FLOWTABLE_RDMA_TX(dev->mdev,
max_modify_header_actions);
} }
static int UVERBS_HANDLER(MLX5_IB_METHOD_FLOW_ACTION_CREATE_MODIFY_HEADER)( static int UVERBS_HANDLER(MLX5_IB_METHOD_FLOW_ACTION_CREATE_MODIFY_HEADER)(

5
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
View file

@ -1894,6 +1894,11 @@ static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
cmd->alloc_dma); cmd->alloc_dma);
} }
static u16 cmdif_rev(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
}
int mlx5_cmd_init(struct mlx5_core_dev *dev) int mlx5_cmd_init(struct mlx5_core_dev *dev)
{ {
int size = sizeof(struct mlx5_cmd_prot_block); int size = sizeof(struct mlx5_cmd_prot_block);

4
drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c
View file

@ -781,6 +781,10 @@ static int mlx5_cmd_modify_header_alloc(struct mlx5_flow_root_namespace *ns,
max_actions = MLX5_CAP_ESW_INGRESS_ACL(dev, max_modify_header_actions); max_actions = MLX5_CAP_ESW_INGRESS_ACL(dev, max_modify_header_actions);
table_type = FS_FT_ESW_INGRESS_ACL; table_type = FS_FT_ESW_INGRESS_ACL;
break; break;
case MLX5_FLOW_NAMESPACE_RDMA_TX:
max_actions = MLX5_CAP_FLOWTABLE_RDMA_TX(dev, max_modify_header_actions);
table_type = FS_FT_RDMA_TX;
break;
default: default:
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }

5
drivers/net/ethernet/mellanox/mlx5/core/main.c
View file

@ -177,6 +177,11 @@ static struct mlx5_profile profile[] = {
#define FW_PRE_INIT_TIMEOUT_MILI 120000 #define FW_PRE_INIT_TIMEOUT_MILI 120000
#define FW_INIT_WARN_MESSAGE_INTERVAL 20000 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
static int fw_initializing(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->initializing) >> 31;
}
static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
u32 warn_time_mili) u32 warn_time_mili)
{ {

1
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
View file

@ -961,7 +961,6 @@ static void dr_ste_copy_mask_misc2(char *mask, struct mlx5dr_match_misc2 *spec)
spec->metadata_reg_c_1 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_1); spec->metadata_reg_c_1 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_1);
spec->metadata_reg_c_0 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_0); spec->metadata_reg_c_0 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_0);
spec->metadata_reg_a = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_a); spec->metadata_reg_a = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_a);
spec->metadata_reg_b = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_b);
} }
static void dr_ste_copy_mask_misc3(char *mask, struct mlx5dr_match_misc3 *spec) static void dr_ste_copy_mask_misc3(char *mask, struct mlx5dr_match_misc3 *spec)

3
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h
View file

@ -554,8 +554,7 @@ struct mlx5dr_match_misc2 {
u32 metadata_reg_c_1; /* metadata_reg_c_1 */ u32 metadata_reg_c_1; /* metadata_reg_c_1 */
u32 metadata_reg_c_0; /* metadata_reg_c_0 */ u32 metadata_reg_c_0; /* metadata_reg_c_0 */
u32 metadata_reg_a; /* metadata_reg_a */ u32 metadata_reg_a; /* metadata_reg_a */
u32 metadata_reg_b; /* metadata_reg_b */ u8 reserved_auto2[12];
u8 reserved_auto2[8];
}; };
struct mlx5dr_match_misc3 { struct mlx5dr_match_misc3 {

10
include/linux/mlx5/driver.h
View file

@ -823,11 +823,6 @@ static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
} }
static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
}
static inline u32 mlx5_base_mkey(const u32 key) static inline u32 mlx5_base_mkey(const u32 key)
{ {
return key & 0xffffff00u; return key & 0xffffff00u;
@ -1012,11 +1007,6 @@ int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
u8 roce_version, u8 roce_l3_type, const u8 *gid, u8 roce_version, u8 roce_l3_type, const u8 *gid,
const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
static inline int fw_initializing(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->initializing) >> 31;
}
static inline u32 mlx5_mkey_to_idx(u32 mkey) static inline u32 mlx5_mkey_to_idx(u32 mkey)
{ {
return mkey >> 8; return mkey >> 8;

30
include/linux/mlx5/mlx5_ifc.h
View file

@ -584,9 +584,7 @@ struct mlx5_ifc_fte_match_set_misc2_bits {
u8 metadata_reg_a[0x20]; u8 metadata_reg_a[0x20];
u8 metadata_reg_b[0x20]; u8 reserved_at_1a0[0x60];
u8 reserved_at_1c0[0x40];
}; };
struct mlx5_ifc_fte_match_set_misc3_bits { struct mlx5_ifc_fte_match_set_misc3_bits {
@ -1210,7 +1208,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_99[0x2]; u8 reserved_at_99[0x2];
u8 log_max_qp[0x5]; u8 log_max_qp[0x5];
u8 reserved_at_a0[0xb]; u8 reserved_at_a0[0x3];
u8 ece_support[0x1];
u8 reserved_at_a4[0x7];
u8 log_max_srq[0x5]; u8 log_max_srq[0x5];
u8 reserved_at_b0[0x10]; u8 reserved_at_b0[0x10];
@ -4220,7 +4220,8 @@ struct mlx5_ifc_rts2rts_qp_out_bits {
u8 syndrome[0x20]; u8 syndrome[0x20];
u8 reserved_at_40[0x40]; u8 reserved_at_40[0x20];
u8 ece[0x20];
}; };
struct mlx5_ifc_rts2rts_qp_in_bits { struct mlx5_ifc_rts2rts_qp_in_bits {
@ -4237,7 +4238,7 @@ struct mlx5_ifc_rts2rts_qp_in_bits {
u8 opt_param_mask[0x20]; u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20]; u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc; struct mlx5_ifc_qpc_bits qpc;
@ -4250,7 +4251,8 @@ struct mlx5_ifc_rtr2rts_qp_out_bits {
u8 syndrome[0x20]; u8 syndrome[0x20];
u8 reserved_at_40[0x40]; u8 reserved_at_40[0x20];
u8 ece[0x20];
}; };
struct mlx5_ifc_rtr2rts_qp_in_bits { struct mlx5_ifc_rtr2rts_qp_in_bits {
@ -4267,7 +4269,7 @@ struct mlx5_ifc_rtr2rts_qp_in_bits {
u8 opt_param_mask[0x20]; u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20]; u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc; struct mlx5_ifc_qpc_bits qpc;
@ -4819,7 +4821,8 @@ struct mlx5_ifc_query_qp_out_bits {
u8 syndrome[0x20]; u8 syndrome[0x20];
u8 reserved_at_40[0x40]; u8 reserved_at_40[0x20];
u8 ece[0x20];
u8 opt_param_mask[0x20]; u8 opt_param_mask[0x20];
@ -6584,7 +6587,8 @@ struct mlx5_ifc_init2rtr_qp_out_bits {
u8 syndrome[0x20]; u8 syndrome[0x20];
u8 reserved_at_40[0x40]; u8 reserved_at_40[0x20];
u8 ece[0x20];
}; };
struct mlx5_ifc_init2rtr_qp_in_bits { struct mlx5_ifc_init2rtr_qp_in_bits {
@ -6601,7 +6605,7 @@ struct mlx5_ifc_init2rtr_qp_in_bits {
u8 opt_param_mask[0x20]; u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20]; u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc; struct mlx5_ifc_qpc_bits qpc;
@ -7697,7 +7701,7 @@ struct mlx5_ifc_create_qp_out_bits {
u8 reserved_at_40[0x8]; u8 reserved_at_40[0x8];
u8 qpn[0x18]; u8 qpn[0x18];
u8 reserved_at_60[0x20]; u8 ece[0x20];
}; };
struct mlx5_ifc_create_qp_in_bits { struct mlx5_ifc_create_qp_in_bits {
@ -7711,7 +7715,7 @@ struct mlx5_ifc_create_qp_in_bits {
u8 opt_param_mask[0x20]; u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20]; u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc; struct mlx5_ifc_qpc_bits qpc;