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Blackfin: work around anomaly 05000287

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Make sure we work around anomaly 05000287 by configuring different port
preferences for the data cache.

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Graf Yang 2009-05-08 07:42:12 +00:00 committed by Mike Frysinger
parent a9a59e3096
commit e522c8466d
1 changed files with 8 additions and 1 deletions
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9
arch/blackfin/kernel/cplb-mpu/cacheinit.c
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@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
}
ctrl = bfin_read_DMEM_CONTROL();
ctrl |= DMEM_CNTR;
/*
* Anomaly notes:
* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
* register, so that the port preferences for DAG0 and DAG1 are set
* to port B
*/
ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
bfin_write_DMEM_CONTROL(ctrl);
SSYNC();
}