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Blackfin: work around anomaly 05000287
Make sure we work around anomaly 05000287 by configuring different port preferences for the data cache. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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1 changed files with 8 additions and 1 deletions
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@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
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}
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ctrl = bfin_read_DMEM_CONTROL();
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ctrl |= DMEM_CNTR;
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/*
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* Anomaly notes:
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* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
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* register, so that the port preferences for DAG0 and DAG1 are set
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* to port B
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*/
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ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
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bfin_write_DMEM_CONTROL(ctrl);
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SSYNC();
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}
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