mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-28 20:02:17 +00:00
dt-bindings: clock: tegra: Add IDs for OSC clocks
Tegra has OSC, OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are the possible parents of Tegra PMC clocks clk_out_1, clk_out_2, and clk_out_3 for Tegra30 through Tegra210. So, this patch adds ids for these clocks. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
parent
bb6d3fb354
commit
e5377ab288
4 changed files with 12 additions and 4 deletions
|
@ -228,6 +228,8 @@
|
|||
#define TEGRA114_CLK_CLK_M 201
|
||||
#define TEGRA114_CLK_CLK_M_DIV2 202
|
||||
#define TEGRA114_CLK_CLK_M_DIV4 203
|
||||
#define TEGRA114_CLK_OSC_DIV2 202
|
||||
#define TEGRA114_CLK_OSC_DIV4 203
|
||||
#define TEGRA114_CLK_PLL_REF 204
|
||||
#define TEGRA114_CLK_PLL_C 205
|
||||
#define TEGRA114_CLK_PLL_C_OUT1 206
|
||||
|
@ -274,7 +276,7 @@
|
|||
#define TEGRA114_CLK_CLK_OUT_2 246
|
||||
#define TEGRA114_CLK_CLK_OUT_3 247
|
||||
#define TEGRA114_CLK_BLINK 248
|
||||
/* 249 */
|
||||
#define TEGRA114_CLK_OSC 249
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
#define TEGRA114_CLK_XUSB_HOST_SRC 252
|
||||
|
|
|
@ -227,6 +227,8 @@
|
|||
#define TEGRA124_CLK_CLK_M 201
|
||||
#define TEGRA124_CLK_CLK_M_DIV2 202
|
||||
#define TEGRA124_CLK_CLK_M_DIV4 203
|
||||
#define TEGRA124_CLK_OSC_DIV2 202
|
||||
#define TEGRA124_CLK_OSC_DIV4 203
|
||||
#define TEGRA124_CLK_PLL_REF 204
|
||||
#define TEGRA124_CLK_PLL_C 205
|
||||
#define TEGRA124_CLK_PLL_C_OUT1 206
|
||||
|
@ -273,7 +275,7 @@
|
|||
#define TEGRA124_CLK_CLK_OUT_2 246
|
||||
#define TEGRA124_CLK_CLK_OUT_3 247
|
||||
#define TEGRA124_CLK_BLINK 248
|
||||
/* 249 */
|
||||
#define TEGRA124_CLK_OSC 249
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
#define TEGRA124_CLK_XUSB_HOST_SRC 252
|
||||
|
|
|
@ -262,6 +262,8 @@
|
|||
#define TEGRA210_CLK_CLK_M 233
|
||||
#define TEGRA210_CLK_CLK_M_DIV2 234
|
||||
#define TEGRA210_CLK_CLK_M_DIV4 235
|
||||
#define TEGRA210_CLK_OSC_DIV2 234
|
||||
#define TEGRA210_CLK_OSC_DIV4 235
|
||||
#define TEGRA210_CLK_PLL_REF 236
|
||||
#define TEGRA210_CLK_PLL_C 237
|
||||
#define TEGRA210_CLK_PLL_C_OUT1 238
|
||||
|
@ -355,7 +357,7 @@
|
|||
#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
|
||||
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
|
||||
/* 325 */
|
||||
/* 326 */
|
||||
#define TEGRA210_CLK_OSC 326
|
||||
/* 327 */
|
||||
/* 328 */
|
||||
/* 329 */
|
||||
|
|
|
@ -196,6 +196,8 @@
|
|||
#define TEGRA30_CLK_CLK_M 171
|
||||
#define TEGRA30_CLK_CLK_M_DIV2 172
|
||||
#define TEGRA30_CLK_CLK_M_DIV4 173
|
||||
#define TEGRA30_CLK_OSC_DIV2 172
|
||||
#define TEGRA30_CLK_OSC_DIV4 173
|
||||
#define TEGRA30_CLK_PLL_REF 174
|
||||
#define TEGRA30_CLK_PLL_C 175
|
||||
#define TEGRA30_CLK_PLL_C_OUT1 176
|
||||
|
@ -243,7 +245,7 @@
|
|||
#define TEGRA30_CLK_HCLK 217
|
||||
#define TEGRA30_CLK_PCLK 218
|
||||
/* 219 */
|
||||
/* 220 */
|
||||
#define TEGRA30_CLK_OSC 220
|
||||
/* 221 */
|
||||
/* 222 */
|
||||
/* 223 */
|
||||
|
|
Loading…
Reference in a new issue