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net/mlx4_core: set port QoS attributes
Adding QoS firmware commands: - mlx4_en_SET_PORT_PRIO2TC - set UP <=> TC - mlx4_en_SET_PORT_SCHEDULER - set promised BW, max BW and PG number Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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5 changed files with 91 additions and 0 deletions
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@ -39,6 +39,8 @@
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#define SET_PORT_PROMISC_SHIFT 31
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#define SET_PORT_MC_PROMISC_SHIFT 30
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#define MLX4_EN_NUM_TC 8
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#define VLAN_FLTR_SIZE 128
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struct mlx4_set_vlan_fltr_mbox {
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__be32 entry[VLAN_FLTR_SIZE];
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@ -53,6 +53,26 @@
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#define DRV_VERSION "1.1"
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#define DRV_RELDATE "Dec, 2011"
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#define MLX4_NUM_UP 8
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#define MLX4_NUM_TC 8
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#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
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#define MLX4_RATELIMIT_DEFAULT 0xffff
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struct mlx4_set_port_prio2tc_context {
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u8 prio2tc[4];
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};
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struct mlx4_port_scheduler_tc_cfg_be {
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__be16 pg;
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__be16 bw_precentage;
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__be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
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__be16 max_bw_value;
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};
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struct mlx4_set_port_scheduler_context {
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struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
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};
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enum {
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MLX4_HCR_BASE = 0x80680,
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MLX4_HCR_SIZE = 0x0001c,
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@ -834,6 +834,68 @@ int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
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}
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EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
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int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc)
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{
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_set_port_prio2tc_context *context;
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int err;
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u32 in_mod;
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int i;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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context = mailbox->buf;
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memset(context, 0, sizeof *context);
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for (i = 0; i < MLX4_NUM_UP; i += 2)
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context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1];
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in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port;
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err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
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MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC);
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int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
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u8 *pg, u16 *ratelimit)
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{
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_set_port_scheduler_context *context;
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int err;
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u32 in_mod;
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int i;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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context = mailbox->buf;
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memset(context, 0, sizeof *context);
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for (i = 0; i < MLX4_NUM_TC; i++) {
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struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
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u16 r = ratelimit && ratelimit[i] ? ratelimit[i] :
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MLX4_RATELIMIT_DEFAULT;
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tc->pg = htons(pg[i]);
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tc->bw_precentage = htons(tc_tx_bw[i]);
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tc->max_bw_units = htons(MLX4_RATELIMIT_UNITS);
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tc->max_bw_value = htons(r);
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}
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in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port;
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err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
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MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER);
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int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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@ -150,6 +150,10 @@ enum {
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/* statistics commands */
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MLX4_CMD_QUERY_IF_STAT = 0X54,
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MLX4_CMD_SET_IF_STAT = 0X55,
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/* set port opcode modifiers */
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MLX4_SET_PORT_PRIO2TC = 0x8,
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MLX4_SET_PORT_SCHEDULER = 0x9,
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};
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enum {
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@ -628,6 +628,9 @@ int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
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u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
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int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
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u8 promisc);
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int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
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int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
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u8 *pg, u16 *ratelimit);
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int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
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int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
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void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
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