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Merge branch 'drm-fixes-3.7' of git://people.freedesktop.org/~agd5f/linux
Just a single pll/crtc regression fix. * 'drm-fixes-3.7' of git://people.freedesktop.org/~agd5f/linux: radeon: fix pll/ctrc mapping on dce2 and dce3 hardware
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commit
e548a83c34
1 changed files with 14 additions and 34 deletions
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@ -1696,42 +1696,22 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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return ATOM_PPLL2;
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DRM_ERROR("unable to allocate a PPLL\n");
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return ATOM_PPLL_INVALID;
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} else if (ASIC_IS_AVIVO(rdev)) {
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/* in DP mode, the DP ref clock can come from either PPLL
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* depending on the asic:
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* DCE3: PPLL1 or PPLL2
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*/
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if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
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/* use the same PPLL for all DP monitors */
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pll = radeon_get_shared_dp_ppll(crtc);
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if (pll != ATOM_PPLL_INVALID)
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return pll;
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} else {
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/* use the same PPLL for all monitors with the same clock */
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pll = radeon_get_shared_nondp_ppll(crtc);
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if (pll != ATOM_PPLL_INVALID)
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return pll;
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}
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/* all other cases */
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pll_in_use = radeon_get_pll_use_mask(crtc);
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/* the order shouldn't matter here, but we probably
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* need this until we have atomic modeset
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*/
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if (rdev->flags & RADEON_IS_IGP) {
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if (!(pll_in_use & (1 << ATOM_PPLL1)))
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return ATOM_PPLL1;
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if (!(pll_in_use & (1 << ATOM_PPLL2)))
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return ATOM_PPLL2;
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} else {
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if (!(pll_in_use & (1 << ATOM_PPLL2)))
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return ATOM_PPLL2;
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if (!(pll_in_use & (1 << ATOM_PPLL1)))
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return ATOM_PPLL1;
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}
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DRM_ERROR("unable to allocate a PPLL\n");
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return ATOM_PPLL_INVALID;
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} else {
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/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
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/* some atombios (observed in some DCE2/DCE3) code have a bug,
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* the matching btw pll and crtc is done through
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* PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
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* pll (1 or 2) to select which register to write. ie if using
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* pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
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* it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
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* choose which value to write. Which is reverse order from
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* register logic. So only case that works is when pllid is
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* same as crtcid or when both pll and crtc are enabled and
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* both use same clock.
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*
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* So just return crtc id as if crtc and pll were hard linked
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* together even if they aren't
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*/
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return radeon_crtc->crtc_id;
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}
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}
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