sparc64: Implement NMI watchdog on capable cpus.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
c3cf5e8cc5
commit
e5553a6d04
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@ -17,7 +17,7 @@
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typedef struct {
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/* Dcache line 1 */
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unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
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unsigned int __pad0;
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unsigned int __nmi_count;
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unsigned long clock_tick; /* %tick's per second */
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unsigned long __pad;
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unsigned int __pad1;
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@ -66,9 +66,6 @@ extern void virt_irq_free(unsigned int virt_irq);
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extern void __init init_IRQ(void);
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extern void fixup_irqs(void);
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extern int register_perfctr_intr(void (*handler)(struct pt_regs *));
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extern void release_perfctr_intr(void (*handler)(struct pt_regs *));
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static inline void set_softint(unsigned long bits)
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{
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__asm__ __volatile__("wr %0, 0x0, %%set_softint"
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@ -98,5 +95,6 @@ void __trigger_all_cpu_backtrace(void);
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extern void *hardirq_stack[NR_CPUS];
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extern void *softirq_stack[NR_CPUS];
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#define __ARCH_HAS_DO_SOFTIRQ
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#define ARCH_HAS_NMI_WATCHDOG
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#endif
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@ -14,6 +14,8 @@ enum die_val {
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DIE_TRAP,
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DIE_TRAP_TL1,
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DIE_CALL,
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DIE_NMI,
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DIE_NMIWATCHDOG,
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};
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#endif
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@ -0,0 +1,10 @@
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#ifndef __NMI_H
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#define __NMI_H
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extern int __init nmi_init(void);
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extern void perfctr_irq(int irq, struct pt_regs *regs);
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extern void nmi_adjust_hz(unsigned int new_hz);
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extern int nmi_usable;
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#endif /* __NMI_H */
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@ -27,4 +27,20 @@ extern void schedule_deferred_pcr_work(void);
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#define PCR_N2_SL1_SHIFT 27
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#define PCR_N2_OV1 0x80000000
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extern unsigned int picl_shift;
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/* In order to commonize as much of the implementation as
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* possible, we use PICH as our counter. Mostly this is
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* to accomodate Niagara-1 which can only count insn cycles
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* in PICH.
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*/
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static inline u64 picl_value(unsigned int nmi_hz)
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{
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u32 delta = local_cpu_data().clock_tick / (nmi_hz << picl_shift);
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return ((u64)((0 - delta) & 0xffffffff)) << 32;
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}
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extern u64 pcr_enable;
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#endif /* __PCR_H */
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@ -53,6 +53,7 @@ obj-$(CONFIG_SPARC64) += hvapi.o
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obj-$(CONFIG_SPARC64) += sstate.o
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obj-$(CONFIG_SPARC64) += mdesc.o
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obj-$(CONFIG_SPARC64) += pcr.o
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obj-$(CONFIG_SPARC64) += nmi.o
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# sparc32 do not use GENERIC_HARDIRQS but uses the generic devres implementation
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obj-$(CONFIG_SPARC32) += devres.o
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@ -196,6 +196,11 @@ int show_interrupts(struct seq_file *p, void *v)
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seq_putc(p, '\n');
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skip:
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spin_unlock_irqrestore(&irq_desc[i].lock, flags);
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} else if (i == NR_IRQS) {
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seq_printf(p, "NMI: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
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seq_printf(p, " Non-maskable interrupts\n");
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}
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return 0;
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}
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@ -778,69 +783,6 @@ void do_softirq(void)
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local_irq_restore(flags);
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}
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static void unhandled_perf_irq(struct pt_regs *regs)
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{
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unsigned long pcr, pic;
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read_pcr(pcr);
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read_pic(pic);
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write_pcr(0);
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printk(KERN_EMERG "CPU %d: Got unexpected perf counter IRQ.\n",
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smp_processor_id());
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printk(KERN_EMERG "CPU %d: PCR[%016lx] PIC[%016lx]\n",
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smp_processor_id(), pcr, pic);
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}
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/* Almost a direct copy of the powerpc PMC code. */
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static DEFINE_SPINLOCK(perf_irq_lock);
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static void *perf_irq_owner_caller; /* mostly for debugging */
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static void (*perf_irq)(struct pt_regs *regs) = unhandled_perf_irq;
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/* Invoked from level 15 PIL handler in trap table. */
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void perfctr_irq(int irq, struct pt_regs *regs)
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{
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clear_softint(1 << irq);
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perf_irq(regs);
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}
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int register_perfctr_intr(void (*handler)(struct pt_regs *))
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{
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int ret;
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if (!handler)
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return -EINVAL;
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spin_lock(&perf_irq_lock);
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if (perf_irq != unhandled_perf_irq) {
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printk(KERN_WARNING "register_perfctr_intr: "
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"perf IRQ busy (reserved by caller %p)\n",
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perf_irq_owner_caller);
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ret = -EBUSY;
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goto out;
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}
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perf_irq_owner_caller = __builtin_return_address(0);
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perf_irq = handler;
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ret = 0;
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out:
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spin_unlock(&perf_irq_lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(register_perfctr_intr);
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void release_perfctr_intr(void (*handler)(struct pt_regs *))
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{
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spin_lock(&perf_irq_lock);
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perf_irq_owner_caller = NULL;
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perf_irq = unhandled_perf_irq;
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spin_unlock(&perf_irq_lock);
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}
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EXPORT_SYMBOL_GPL(release_perfctr_intr);
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#ifdef CONFIG_HOTPLUG_CPU
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void fixup_irqs(void)
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{
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@ -0,0 +1,224 @@
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/* Pseudo NMI support on sparc64 systems.
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*
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* Copyright (C) 2009 David S. Miller <davem@davemloft.net>
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*
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* The NMI watchdog support and infrastructure is based almost
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* entirely upon the x86 NMI support code.
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*/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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#include <linux/nmi.h>
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#include <linux/module.h>
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#include <linux/kprobes.h>
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#include <linux/kernel_stat.h>
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#include <linux/slab.h>
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#include <linux/kdebug.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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#include <asm/ptrace.h>
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#include <asm/local.h>
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#include <asm/pcr.h>
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/* We don't have a real NMI on sparc64, but we can fake one
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* up using profiling counter overflow interrupts and interrupt
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* levels.
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*
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* The profile overflow interrupts at level 15, so we use
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* level 14 as our IRQ off level.
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*/
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static int nmi_watchdog_active;
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static int panic_on_timeout;
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int nmi_usable;
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EXPORT_SYMBOL_GPL(nmi_usable);
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static unsigned int nmi_hz = HZ;
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static DEFINE_PER_CPU(unsigned int, last_irq_sum);
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static DEFINE_PER_CPU(local_t, alert_counter);
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static DEFINE_PER_CPU(int, nmi_touch);
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void touch_nmi_watchdog(void)
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{
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if (nmi_watchdog_active) {
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int cpu;
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for_each_present_cpu(cpu) {
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if (per_cpu(nmi_touch, cpu) != 1)
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per_cpu(nmi_touch, cpu) = 1;
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}
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}
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touch_softlockup_watchdog();
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}
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EXPORT_SYMBOL(touch_nmi_watchdog);
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static void die_nmi(const char *str, struct pt_regs *regs, int do_panic)
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{
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if (notify_die(DIE_NMIWATCHDOG, str, regs, 0,
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pt_regs_trap_type(regs), SIGINT) == NOTIFY_STOP)
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return;
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console_verbose();
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bust_spinlocks(1);
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printk(KERN_EMERG "%s", str);
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printk(" on CPU%d, ip %08lx, registers:\n",
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smp_processor_id(), regs->tpc);
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show_regs(regs);
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bust_spinlocks(0);
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if (do_panic || panic_on_oops)
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panic("Non maskable interrupt");
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local_irq_enable();
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do_exit(SIGBUS);
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}
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notrace __kprobes void perfctr_irq(int irq, struct pt_regs *regs)
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{
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unsigned int sum, touched = 0;
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int cpu = smp_processor_id();
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clear_softint(1 << irq);
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pcr_ops->write(PCR_PIC_PRIV);
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local_cpu_data().__nmi_count++;
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if (notify_die(DIE_NMI, "nmi", regs, 0,
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pt_regs_trap_type(regs), SIGINT) == NOTIFY_STOP)
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touched = 1;
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sum = kstat_cpu(cpu).irqs[0];
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if (__get_cpu_var(nmi_touch)) {
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__get_cpu_var(nmi_touch) = 0;
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touched = 1;
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}
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if (!touched && __get_cpu_var(last_irq_sum) == sum) {
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local_inc(&__get_cpu_var(alert_counter));
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if (local_read(&__get_cpu_var(alert_counter)) == 5 * nmi_hz)
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die_nmi("BUG: NMI Watchdog detected LOCKUP",
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regs, panic_on_timeout);
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} else {
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__get_cpu_var(last_irq_sum) = sum;
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local_set(&__get_cpu_var(alert_counter), 0);
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}
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if (nmi_usable) {
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write_pic(picl_value(nmi_hz));
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pcr_ops->write(pcr_enable);
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}
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}
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static inline unsigned int get_nmi_count(int cpu)
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{
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return cpu_data(cpu).__nmi_count;
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}
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static int endflag __initdata;
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static __init void nmi_cpu_busy(void *data)
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{
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local_irq_enable_in_hardirq();
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while (endflag == 0)
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mb();
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}
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static void report_broken_nmi(int cpu, int *prev_nmi_count)
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{
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printk(KERN_CONT "\n");
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printk(KERN_WARNING
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"WARNING: CPU#%d: NMI appears to be stuck (%d->%d)!\n",
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cpu, prev_nmi_count[cpu], get_nmi_count(cpu));
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printk(KERN_WARNING
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"Please report this to bugzilla.kernel.org,\n");
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printk(KERN_WARNING
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"and attach the output of the 'dmesg' command.\n");
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nmi_usable = 0;
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}
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static void stop_watchdog(void *unused)
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{
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pcr_ops->write(PCR_PIC_PRIV);
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}
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static int __init check_nmi_watchdog(void)
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{
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unsigned int *prev_nmi_count;
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int cpu, err;
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prev_nmi_count = kmalloc(nr_cpu_ids * sizeof(unsigned int), GFP_KERNEL);
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if (!prev_nmi_count) {
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err = -ENOMEM;
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goto error;
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}
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printk(KERN_INFO "Testing NMI watchdog ... ");
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smp_call_function(nmi_cpu_busy, (void *)&endflag, 0);
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for_each_possible_cpu(cpu)
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prev_nmi_count[cpu] = get_nmi_count(cpu);
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local_irq_enable();
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mdelay((20 * 1000) / nmi_hz); /* wait 20 ticks */
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for_each_online_cpu(cpu) {
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if (get_nmi_count(cpu) - prev_nmi_count[cpu] <= 5)
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report_broken_nmi(cpu, prev_nmi_count);
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}
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endflag = 1;
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if (!nmi_usable) {
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kfree(prev_nmi_count);
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err = -ENODEV;
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goto error;
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}
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printk("OK.\n");
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nmi_hz = 1;
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kfree(prev_nmi_count);
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return 0;
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error:
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on_each_cpu(stop_watchdog, NULL, 1);
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return err;
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}
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static void start_watchdog(void *unused)
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{
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pcr_ops->write(PCR_PIC_PRIV);
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write_pic(picl_value(nmi_hz));
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pcr_ops->write(pcr_enable);
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}
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void nmi_adjust_hz(unsigned int new_hz)
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{
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nmi_hz = new_hz;
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on_each_cpu(start_watchdog, NULL, 1);
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}
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EXPORT_SYMBOL_GPL(nmi_adjust_hz);
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int __init nmi_init(void)
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{
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nmi_usable = 1;
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on_each_cpu(start_watchdog, NULL, 1);
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return check_nmi_watchdog();
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}
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static int __init setup_nmi_watchdog(char *str)
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{
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if (!strncmp(str, "panic", 5))
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panic_on_timeout = 1;
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return 0;
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}
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__setup("nmi_watchdog=", setup_nmi_watchdog);
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@ -9,12 +9,22 @@
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#include <asm/pil.h>
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#include <asm/pcr.h>
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#include <asm/nmi.h>
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/* This code is shared between various users of the performance
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* counters. Users will be oprofile, pseudo-NMI watchdog, and the
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* perf_counter support layer.
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*/
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#define PCR_SUN4U_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE)
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#define PCR_N2_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE | \
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PCR_N2_TOE_OV1 | \
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(2 << PCR_N2_SL1_SHIFT) | \
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(0xff << PCR_N2_MASK1_SHIFT))
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u64 pcr_enable;
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unsigned int picl_shift;
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/* Performance counter interrupts run unmasked at PIL level 15.
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* Therefore we can't do things like wakeups and other work
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* that expects IRQ disabling to be adhered to in locking etc.
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@ -117,12 +127,15 @@ int __init pcr_arch_init(void)
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switch (tlb_type) {
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case hypervisor:
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pcr_ops = &n2_pcr_ops;
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pcr_enable = PCR_N2_ENABLE;
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picl_shift = 2;
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break;
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case spitfire:
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case cheetah:
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case cheetah_plus:
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case spitfire:
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pcr_ops = &direct_pcr_ops;
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pcr_enable = PCR_SUN4U_ENABLE;
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break;
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default:
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@ -130,7 +143,7 @@ int __init pcr_arch_init(void)
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goto out_unregister;
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}
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return 0;
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return nmi_init();
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out_unregister:
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unregister_perf_hsvc();
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@ -13,117 +13,57 @@
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#include <linux/init.h>
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#ifdef CONFIG_SPARC64
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#include <asm/hypervisor.h>
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#include <asm/spitfire.h>
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#include <asm/cpudata.h>
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#include <asm/irq.h>
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#include <asm/pcr.h>
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#include <linux/notifier.h>
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#include <linux/rcupdate.h>
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#include <linux/kdebug.h>
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#include <asm/nmi.h>
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static int nmi_enabled;
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/* In order to commonize as much of the implementation as
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* possible, we use PICH as our counter. Mostly this is
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* to accomodate Niagara-1 which can only count insn cycles
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* in PICH.
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*/
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static u64 picl_value(void)
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static int profile_timer_exceptions_notify(struct notifier_block *self,
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unsigned long val, void *data)
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{
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u32 delta = local_cpu_data().clock_tick / HZ;
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struct die_args *args = (struct die_args *)data;
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int ret = NOTIFY_DONE;
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return ((u64)((0 - delta) & 0xffffffff)) << 32;
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}
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#define PCR_SUN4U_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE)
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#define PCR_N2_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE | \
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PCR_N2_TOE_OV1 | \
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(2 << PCR_N2_SL1_SHIFT) | \
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(0xff << PCR_N2_MASK1_SHIFT))
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static u64 pcr_enable;
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|
||||
static void nmi_handler(struct pt_regs *regs)
|
||||
{
|
||||
pcr_ops->write(PCR_PIC_PRIV);
|
||||
|
||||
if (nmi_enabled) {
|
||||
oprofile_add_sample(regs, 0);
|
||||
|
||||
write_pic(picl_value());
|
||||
pcr_ops->write(pcr_enable);
|
||||
}
|
||||
}
|
||||
|
||||
/* We count "clock cycle" events in the lower 32-bit PIC.
|
||||
* Then configure it such that it overflows every HZ, and thus
|
||||
* generates a level 15 interrupt at that frequency.
|
||||
*/
|
||||
static void cpu_nmi_start(void *_unused)
|
||||
{
|
||||
pcr_ops->write(PCR_PIC_PRIV);
|
||||
write_pic(picl_value());
|
||||
|
||||
pcr_ops->write(pcr_enable);
|
||||
}
|
||||
|
||||
static void cpu_nmi_stop(void *_unused)
|
||||
{
|
||||
pcr_ops->write(PCR_PIC_PRIV);
|
||||
}
|
||||
|
||||
static int nmi_start(void)
|
||||
{
|
||||
int err = register_perfctr_intr(nmi_handler);
|
||||
|
||||
if (!err) {
|
||||
nmi_enabled = 1;
|
||||
wmb();
|
||||
err = on_each_cpu(cpu_nmi_start, NULL, 1);
|
||||
if (err) {
|
||||
nmi_enabled = 0;
|
||||
wmb();
|
||||
on_each_cpu(cpu_nmi_stop, NULL, 1);
|
||||
release_perfctr_intr(nmi_handler);
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void nmi_stop(void)
|
||||
{
|
||||
nmi_enabled = 0;
|
||||
wmb();
|
||||
|
||||
on_each_cpu(cpu_nmi_stop, NULL, 1);
|
||||
release_perfctr_intr(nmi_handler);
|
||||
synchronize_sched();
|
||||
}
|
||||
|
||||
static int oprofile_nmi_init(struct oprofile_operations *ops)
|
||||
{
|
||||
switch (tlb_type) {
|
||||
case hypervisor:
|
||||
pcr_enable = PCR_N2_ENABLE;
|
||||
switch (val) {
|
||||
case DIE_NMI:
|
||||
oprofile_add_sample(args->regs, 0);
|
||||
ret = NOTIFY_STOP;
|
||||
break;
|
||||
|
||||
case cheetah:
|
||||
case cheetah_plus:
|
||||
pcr_enable = PCR_SUN4U_ENABLE;
|
||||
break;
|
||||
|
||||
default:
|
||||
return -ENODEV;
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
ops->create_files = NULL;
|
||||
ops->setup = NULL;
|
||||
ops->shutdown = NULL;
|
||||
ops->start = nmi_start;
|
||||
ops->stop = nmi_stop;
|
||||
static struct notifier_block profile_timer_exceptions_nb = {
|
||||
.notifier_call = profile_timer_exceptions_notify,
|
||||
};
|
||||
|
||||
static int timer_start(void)
|
||||
{
|
||||
if (register_die_notifier(&profile_timer_exceptions_nb))
|
||||
return 1;
|
||||
nmi_adjust_hz(HZ);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void timer_stop(void)
|
||||
{
|
||||
nmi_adjust_hz(1);
|
||||
unregister_die_notifier(&profile_timer_exceptions_nb);
|
||||
synchronize_sched(); /* Allow already-started NMIs to complete. */
|
||||
}
|
||||
|
||||
static int op_nmi_timer_init(struct oprofile_operations *ops)
|
||||
{
|
||||
if (!nmi_usable)
|
||||
return -ENODEV;
|
||||
|
||||
ops->start = timer_start;
|
||||
ops->stop = timer_stop;
|
||||
ops->cpu_type = "timer";
|
||||
|
||||
printk(KERN_INFO "oprofile: Using perfctr based NMI timer interrupt.\n");
|
||||
|
||||
printk(KERN_INFO "oprofile: Using perfctr NMI timer interrupt.\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -133,7 +73,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
|
|||
int ret = -ENODEV;
|
||||
|
||||
#ifdef CONFIG_SPARC64
|
||||
ret = oprofile_nmi_init(ops);
|
||||
ret = op_nmi_timer_init(ops);
|
||||
if (!ret)
|
||||
return ret;
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue