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ahci: imx: add the imx6qp ahci sata support
- Regarding to imx6q ahci sata, imx6qp ahci sata has the reset mechanism. Add the imx6qp ahci sata support in this commit. - Use the specific reset callback for imx53 sata, and use the default ahci_ops.softreset for the others. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
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parent
34d232eb2d
commit
e5878732a5
3 changed files with 35 additions and 4 deletions
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@ -7,6 +7,7 @@ Required properties:
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- compatible : should be one of the following:
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- "fsl,imx53-ahci" for i.MX53 SATA controller
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- "fsl,imx6q-ahci" for i.MX6Q SATA controller
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- "fsl,imx6qp-ahci" for i.MX6QP SATA controller
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- interrupts : interrupt mapping for SATA IRQ
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- reg : registers mapping
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- clocks : list of clock specifiers, must contain an entry for each
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@ -58,6 +58,7 @@ enum {
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enum ahci_imx_type {
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AHCI_IMX53,
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AHCI_IMX6Q,
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AHCI_IMX6QP,
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};
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struct imx_ahci_priv {
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@ -188,11 +189,26 @@ static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
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static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
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{
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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void __iomem *mmio = hpriv->mmio;
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int timeout = 10;
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u16 val;
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int ret;
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if (imxpriv->type == AHCI_IMX6QP) {
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/* 6qp adds the sata reset mechanism, use it for 6qp sata */
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
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IMX6Q_GPR5_SATA_SW_PD, 0);
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
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IMX6Q_GPR5_SATA_SW_RST, 0);
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udelay(50);
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
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IMX6Q_GPR5_SATA_SW_RST,
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IMX6Q_GPR5_SATA_SW_RST);
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return 0;
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}
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/* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
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ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
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if (ret)
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@ -408,7 +424,7 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
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if (ret < 0)
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goto disable_regulator;
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if (imxpriv->type == AHCI_IMX6Q) {
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if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
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/*
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* set PHY Paremeters, two steps to configure the GPR13,
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* one write for rest of parameters, mask of first write
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@ -459,10 +475,21 @@ static void imx_sata_disable(struct ahci_host_priv *hpriv)
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if (imxpriv->no_device)
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return;
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if (imxpriv->type == AHCI_IMX6Q) {
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switch (imxpriv->type) {
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case AHCI_IMX6QP:
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
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IMX6Q_GPR5_SATA_SW_PD,
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IMX6Q_GPR5_SATA_SW_PD);
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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break;
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case AHCI_IMX6Q:
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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break;
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}
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clk_disable_unprepare(imxpriv->sata_ref_clk);
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@ -513,7 +540,7 @@ static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
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if (imxpriv->type == AHCI_IMX53)
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ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
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else if (imxpriv->type == AHCI_IMX6Q)
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else
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ret = ahci_ops.softreset(link, class, deadline);
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return ret;
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@ -536,6 +563,7 @@ static const struct ata_port_info ahci_imx_port_info = {
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static const struct of_device_id imx_ahci_of_match[] = {
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{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
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{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
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{ .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP },
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{},
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};
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MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
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@ -743,7 +771,7 @@ static int imx_ahci_probe(struct platform_device *pdev)
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return PTR_ERR(imxpriv->ahb_clk);
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}
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if (imxpriv->type == AHCI_IMX6Q) {
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if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
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u32 reg_value;
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imxpriv->gpr = syscon_regmap_lookup_by_compatible(
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@ -243,6 +243,8 @@
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#define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0)
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#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
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#define IMX6Q_GPR5_SATA_SW_PD BIT(10)
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#define IMX6Q_GPR5_SATA_SW_RST BIT(11)
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#define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0)
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#define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4)
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