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pinctrl: cherryview: Allocate IRQ chip dynamic

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Keeping the IRQ chip definition static shares it with multiple instances
of the GPIO chip in the system. This is bad and now we get this warning
from GPIO library:

"detected irqchip that is shared with multiple gpiochips: please fix the driver."

Hence, move the IRQ chip definition from being driver static into the struct
intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance.

This patch is heavily based on the attachment to the bug by Christoph Marz.

BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=202543
Fixes: 6e08d6bbeb ("pinctrl: Add Intel Cherryview/Braswell pin controller support")
Depends-on: 83b9dc1131 ("pinctrl: cherryview: Associate IRQ descriptors to irqdomain")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
Andy Shevchenko 2019-10-24 16:34:41 +03:00
parent 17d49c6258
commit e58e177392
1 changed files with 12 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

24
drivers/pinctrl/intel/pinctrl-cherryview.c
View file

@ -147,6 +147,7 @@ struct chv_pin_context {
* @pctldesc: Pin controller description * @pctldesc: Pin controller description
* @pctldev: Pointer to the pin controller device * @pctldev: Pointer to the pin controller device
* @chip: GPIO chip in this pin controller * @chip: GPIO chip in this pin controller
* @irqchip: IRQ chip in this pin controller
* @regs: MMIO registers * @regs: MMIO registers
* @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
* offset (in GPIO number space) * offset (in GPIO number space)
@ -162,6 +163,7 @@ struct chv_pinctrl {
struct pinctrl_desc pctldesc; struct pinctrl_desc pctldesc;
struct pinctrl_dev *pctldev; struct pinctrl_dev *pctldev;
struct gpio_chip chip; struct gpio_chip chip;
struct irq_chip irqchip;
void __iomem *regs; void __iomem *regs;
unsigned intr_lines[16]; unsigned intr_lines[16];
const struct chv_community *community; const struct chv_community *community;
@ -1466,16 +1468,6 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
return 0; return 0;
} }
static struct irq_chip chv_gpio_irqchip = {
.name = "chv-gpio",
.irq_startup = chv_gpio_irq_startup,
.irq_ack = chv_gpio_irq_ack,
.irq_mask = chv_gpio_irq_mask,
.irq_unmask = chv_gpio_irq_unmask,
.irq_set_type = chv_gpio_irq_type,
.flags = IRQCHIP_SKIP_SET_WAKE,
};
static void chv_gpio_irq_handler(struct irq_desc *desc) static void chv_gpio_irq_handler(struct irq_desc *desc)
{ {
struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct gpio_chip *gc = irq_desc_get_handler_data(desc);
@ -1625,7 +1617,15 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
} }
} }
ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, pctrl->irqchip.name = "chv-gpio";
pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0,
handle_bad_irq, IRQ_TYPE_NONE); handle_bad_irq, IRQ_TYPE_NONE);
if (ret) { if (ret) {
dev_err(pctrl->dev, "failed to add IRQ chip\n"); dev_err(pctrl->dev, "failed to add IRQ chip\n");
@ -1642,7 +1642,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
} }
} }
gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq,
chv_gpio_irq_handler); chv_gpio_irq_handler);
return 0; return 0;
} }