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gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler 

Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
This commit is contained in:
Steven Lee 2021-12-14 12:02:38 +08:00 committed by Bartosz Golaszewski
parent c9e6606c7f
commit e5a7431f5a
1 changed files with 1 additions and 1 deletions
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2
drivers/gpio/gpio-aspeed-sgpio.c
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@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
reg = ioread32(bank_reg(data, bank, reg_irq_status));
for_each_set_bit(p, &reg, 32)
generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
}
chained_irq_exit(ic, desc);