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drm/i915/mtl: Add gmbus and gpio support
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC. From spec we have registers GPIO_CTL[1-5] mapped to native display phys and GPIO_CTL[9-12] are mapped to TC ports. v2: - Drop unused GPIO pins(MattR) BSpec: 49306 Cc: Matt Roper <matthew.d.roper@intel.com> Original Author: Brian J Lovin Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220902060342.151824-6-radhakrishna.sripada@intel.com
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2 changed files with 16 additions and 0 deletions
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@ -117,6 +117,18 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
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[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
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};
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static const struct gmbus_pin gmbus_pins_mtp[] = {
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[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
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[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
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[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
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[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
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[GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
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[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
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[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
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[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
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[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
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};
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static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
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unsigned int pin)
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{
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@ -129,6 +141,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
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} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
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pins = gmbus_pins_dg1;
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size = ARRAY_SIZE(gmbus_pins_dg1);
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} else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
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pins = gmbus_pins_mtp;
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size = ARRAY_SIZE(gmbus_pins_mtp);
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} else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
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pins = gmbus_pins_icp;
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size = ARRAY_SIZE(gmbus_pins_icp);
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@ -24,6 +24,7 @@ struct i2c_adapter;
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#define GMBUS_PIN_2_BXT 2
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#define GMBUS_PIN_3_BXT 3
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#define GMBUS_PIN_4_CNP 4
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#define GMBUS_PIN_5_MTP 5
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#define GMBUS_PIN_9_TC1_ICP 9
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#define GMBUS_PIN_10_TC2_ICP 10
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#define GMBUS_PIN_11_TC3_ICP 11
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