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Blackfin arch: fix the aliased write macros
Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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1 changed files with 2 additions and 2 deletions
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@ -83,9 +83,9 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
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#define bfin_read_SWRST() bfin_read_SICA_SWRST()
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#define bfin_write_SWRST() bfin_write_SICA_SWRST()
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#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
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#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
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#define bfin_write_SYSCR() bfin_write_SICA_SYSCR()
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#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
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/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
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#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
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