mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-24 01:41:39 +00:00
clk: meson: meson8b: add the vclk_en gate clock
HHI_VID_CLK_CNTL[19] is documented as CLK_EN0. This description is the same in the public S912 datasheet and the GXBB driver calls this gate "vclk". Add this gate clock to the Meson8/Meson8b/Meson8m2 clock controller because it's needed to make the video output work. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200629203904.2989007-2-martin.blumenstingl@googlemail.com
This commit is contained in:
parent
d4db5721f3
commit
e653b41131
2 changed files with 27 additions and 6 deletions
|
@ -1204,6 +1204,22 @@ static struct clk_regmap meson8b_vclk_in_en = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vclk_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 19,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vclk_div1_gate = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
|
@ -1213,7 +1229,7 @@ static struct clk_regmap meson8b_vclk_div1_gate = {
|
|||
.name = "vclk_div1_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
&meson8b_vclk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
@ -1227,7 +1243,7 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = {
|
|||
.name = "vclk_div2",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
&meson8b_vclk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
@ -1257,7 +1273,7 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = {
|
|||
.name = "vclk_div4",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
&meson8b_vclk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
@ -1287,7 +1303,7 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = {
|
|||
.name = "vclk_div6",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
&meson8b_vclk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
@ -1317,7 +1333,7 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = {
|
|||
.name = "vclk_div12",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
&meson8b_vclk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
@ -2820,6 +2836,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
|
|||
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
|
||||
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
|
||||
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
|
||||
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
|
||||
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
|
||||
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
|
||||
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
|
||||
|
@ -3025,6 +3042,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
|||
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
|
||||
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
|
||||
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
|
||||
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
|
||||
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
|
||||
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
|
||||
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
|
||||
|
@ -3241,6 +3259,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
|
|||
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
|
||||
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
|
||||
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
|
||||
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
|
||||
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
|
||||
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
|
||||
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
|
||||
|
@ -3443,6 +3462,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
|
|||
&meson8b_vid_pll_final_div,
|
||||
&meson8b_vclk_in_sel,
|
||||
&meson8b_vclk_in_en,
|
||||
&meson8b_vclk_en,
|
||||
&meson8b_vclk_div1_gate,
|
||||
&meson8b_vclk_div2_div_gate,
|
||||
&meson8b_vclk_div4_div_gate,
|
||||
|
|
|
@ -180,8 +180,9 @@
|
|||
#define CLKID_CTS_AMCLK_DIV 208
|
||||
#define CLKID_CTS_MCLK_I958_SEL 210
|
||||
#define CLKID_CTS_MCLK_I958_DIV 211
|
||||
#define CLKID_VCLK_EN 214
|
||||
|
||||
#define CLK_NR_CLKS 214
|
||||
#define CLK_NR_CLKS 215
|
||||
|
||||
/*
|
||||
* include the CLKID and RESETID that have
|
||||
|
|
Loading…
Reference in a new issue