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clk: fixed-factor: Allow for a few clocks to change the parent rate
The only way for a fixed factor clock to change its rate would be to change its parent rate. Since passing blindly CLK_SET_RATE_PARENT might break a lot of platforms that were relying on the fact that the parent rate wouldn't change, introduce a compatible-based whitelist that will allow clocks to opt-in that flag. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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2 changed files with 14 additions and 1 deletions
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@ -14,6 +14,10 @@ Required properties:
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Optional properties:
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- clock-output-names : From common clock binding.
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Some clocks that require special treatments are also handled by that
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driver, with the compatibles:
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- allwinner,sun4i-a10-pll3-2x-clk
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Example:
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clock {
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compatible = "fixed-factor-clock";
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@ -142,6 +142,11 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw)
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EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
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#ifdef CONFIG_OF
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static const struct of_device_id set_rate_parent_matches[] = {
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{ .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
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{ /* Sentinel */ },
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};
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/**
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* of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
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*/
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@ -150,6 +155,7 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
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struct clk *clk;
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const char *clk_name = node->name;
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const char *parent_name;
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unsigned long flags = 0;
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u32 div, mult;
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if (of_property_read_u32(node, "clock-div", &div)) {
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@ -167,7 +173,10 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
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of_property_read_string(node, "clock-output-names", &clk_name);
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parent_name = of_clk_get_parent_name(node, 0);
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clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
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if (of_match_node(set_rate_parent_matches, node))
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flags |= CLK_SET_RATE_PARENT;
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clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
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mult, div);
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if (!IS_ERR(clk))
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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