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clk: qcom: Add MSM8226 Multimedia Clock Controller support
Modify the existing MSM8974 multimedia clock controller driver to support the MMCC found on MSM8226 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220207185411.19118-3-bartosz.dudziak@snejp.pl
This commit is contained in:
parent
ef36263aa0
commit
e6db8c8be7
1 changed files with 201 additions and 5 deletions
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@ -257,6 +257,18 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
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},
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},
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};
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};
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static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(37500000, P_GPLL0, 16, 0, 0),
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F(50000000, P_GPLL0, 12, 0, 0),
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F(75000000, P_GPLL0, 8, 0, 0),
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F(100000000, P_GPLL0, 6, 0, 0),
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F(150000000, P_GPLL0, 4, 0, 0),
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F(200000000, P_MMPLL0, 4, 0, 0),
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F(266666666, P_MMPLL0, 3, 0, 0),
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{ }
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};
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static struct freq_tbl ftbl_mmss_axi_clk[] = {
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static struct freq_tbl ftbl_mmss_axi_clk[] = {
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F( 19200000, P_XO, 1, 0, 0),
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F( 19200000, P_XO, 1, 0, 0),
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F( 37500000, P_GPLL0, 16, 0, 0),
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F( 37500000, P_GPLL0, 16, 0, 0),
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@ -364,6 +376,23 @@ static struct clk_rcg2 csi3_clk_src = {
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},
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},
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};
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};
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static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
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F(37500000, P_GPLL0, 16, 0, 0),
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F(50000000, P_GPLL0, 12, 0, 0),
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F(60000000, P_GPLL0, 10, 0, 0),
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F(80000000, P_GPLL0, 7.5, 0, 0),
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F(100000000, P_GPLL0, 6, 0, 0),
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F(109090000, P_GPLL0, 5.5, 0, 0),
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F(133330000, P_GPLL0, 4.5, 0, 0),
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F(150000000, P_GPLL0, 4, 0, 0),
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F(200000000, P_GPLL0, 3, 0, 0),
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F(228570000, P_MMPLL0, 3.5, 0, 0),
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F(266670000, P_MMPLL0, 3, 0, 0),
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F(320000000, P_MMPLL0, 2.5, 0, 0),
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F(400000000, P_MMPLL0, 2, 0, 0),
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{ }
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};
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static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
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static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
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F(37500000, P_GPLL0, 16, 0, 0),
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F(37500000, P_GPLL0, 16, 0, 0),
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F(50000000, P_GPLL0, 12, 0, 0),
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F(50000000, P_GPLL0, 12, 0, 0),
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@ -407,6 +436,18 @@ static struct clk_rcg2 vfe1_clk_src = {
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},
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},
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};
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};
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static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
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F(37500000, P_GPLL0, 16, 0, 0),
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F(60000000, P_GPLL0, 10, 0, 0),
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F(75000000, P_GPLL0, 8, 0, 0),
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F(92310000, P_GPLL0, 6.5, 0, 0),
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F(100000000, P_GPLL0, 6, 0, 0),
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F(133330000, P_MMPLL0, 6, 0, 0),
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F(177780000, P_MMPLL0, 4.5, 0, 0),
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F(200000000, P_MMPLL0, 4, 0, 0),
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{ }
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};
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static struct freq_tbl ftbl_mdss_mdp_clk[] = {
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static struct freq_tbl ftbl_mdss_mdp_clk[] = {
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F(37500000, P_GPLL0, 16, 0, 0),
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F(37500000, P_GPLL0, 16, 0, 0),
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F(60000000, P_GPLL0, 10, 0, 0),
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F(60000000, P_GPLL0, 10, 0, 0),
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@ -513,6 +554,14 @@ static struct clk_rcg2 pclk1_clk_src = {
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},
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},
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};
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};
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static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
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F(66700000, P_GPLL0, 9, 0, 0),
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F(100000000, P_GPLL0, 6, 0, 0),
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F(133330000, P_MMPLL0, 6, 0, 0),
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F(160000000, P_MMPLL0, 5, 0, 0),
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{ }
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};
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static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
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static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
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F(50000000, P_GPLL0, 12, 0, 0),
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F(50000000, P_GPLL0, 12, 0, 0),
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F(100000000, P_GPLL0, 6, 0, 0),
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F(100000000, P_GPLL0, 6, 0, 0),
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@ -593,6 +642,13 @@ static struct clk_rcg2 camss_gp1_clk_src = {
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},
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},
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};
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};
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static struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(24000000, P_GPLL0, 5, 1, 5),
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F(66670000, P_GPLL0, 9, 0, 0),
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{ }
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};
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static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
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static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
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F(4800000, P_XO, 4, 0, 0),
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F(4800000, P_XO, 4, 0, 0),
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F(6000000, P_GPLL0, 10, 1, 10),
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F(6000000, P_GPLL0, 10, 1, 10),
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@ -705,6 +761,15 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
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},
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},
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};
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};
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static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
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F(133330000, P_GPLL0, 4.5, 0, 0),
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F(150000000, P_GPLL0, 4, 0, 0),
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F(266670000, P_MMPLL0, 3, 0, 0),
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F(320000000, P_MMPLL0, 2.5, 0, 0),
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F(400000000, P_MMPLL0, 2, 0, 0),
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{ }
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};
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static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
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static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
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F(133330000, P_GPLL0, 4.5, 0, 0),
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F(133330000, P_GPLL0, 4.5, 0, 0),
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F(266670000, P_MMPLL0, 3, 0, 0),
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F(266670000, P_MMPLL0, 3, 0, 0),
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@ -2366,6 +2431,116 @@ static struct gdsc oxilicx_gdsc = {
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.pwrsts = PWRSTS_OFF_ON,
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.pwrsts = PWRSTS_OFF_ON,
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};
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};
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static struct clk_regmap *mmcc_msm8226_clocks[] = {
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[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
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[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
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[MMPLL0] = &mmpll0.clkr,
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[MMPLL0_VOTE] = &mmpll0_vote,
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[MMPLL1] = &mmpll1.clkr,
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[MMPLL1_VOTE] = &mmpll1_vote,
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[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
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[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
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[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
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[MDP_CLK_SRC] = &mdp_clk_src.clkr,
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[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
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[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
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[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
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[CCI_CLK_SRC] = &cci_clk_src.clkr,
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[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
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[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
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[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
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[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
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[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
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[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
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[CPP_CLK_SRC] = &cpp_clk_src.clkr,
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[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
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[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
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[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
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[CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
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[CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
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[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
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[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
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[CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
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[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
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[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
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[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
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[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
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[CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
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[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
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[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
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[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
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[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
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[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
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[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
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[CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
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[CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
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[CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
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[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
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[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
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[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
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[CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
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[CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
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[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
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[CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
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[CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
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[CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
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[CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
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[CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
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[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
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[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
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[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
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[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
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[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
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[MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
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[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
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[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
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[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
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[MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
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[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
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[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
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[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
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[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
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[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
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[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
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[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
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[OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
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[VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
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[VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
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[VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
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};
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static const struct qcom_reset_map mmcc_msm8226_resets[] = {
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[SPDM_RESET] = { 0x0200 },
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[SPDM_RM_RESET] = { 0x0300 },
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[VENUS0_RESET] = { 0x1020 },
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[MDSS_RESET] = { 0x2300 },
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};
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static struct gdsc *mmcc_msm8226_gdscs[] = {
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[VENUS0_GDSC] = &venus0_gdsc,
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[MDSS_GDSC] = &mdss_gdsc,
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[CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
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[CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
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};
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static const struct regmap_config mmcc_msm8226_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x5104,
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.fast_io = true,
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};
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static const struct qcom_cc_desc mmcc_msm8226_desc = {
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.config = &mmcc_msm8226_regmap_config,
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.clks = mmcc_msm8226_clocks,
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.num_clks = ARRAY_SIZE(mmcc_msm8226_clocks),
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.resets = mmcc_msm8226_resets,
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.num_resets = ARRAY_SIZE(mmcc_msm8226_resets),
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.gdscs = mmcc_msm8226_gdscs,
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.num_gdscs = ARRAY_SIZE(mmcc_msm8226_gdscs),
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};
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static struct clk_regmap *mmcc_msm8974_clocks[] = {
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static struct clk_regmap *mmcc_msm8974_clocks[] = {
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[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
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[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
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[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
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[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
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@ -2569,23 +2744,44 @@ static const struct qcom_cc_desc mmcc_msm8974_desc = {
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};
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};
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static const struct of_device_id mmcc_msm8974_match_table[] = {
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static const struct of_device_id mmcc_msm8974_match_table[] = {
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{ .compatible = "qcom,mmcc-msm8974" },
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{ .compatible = "qcom,mmcc-msm8226", .data = &mmcc_msm8226_desc },
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{ .compatible = "qcom,mmcc-msm8974", .data = &mmcc_msm8974_desc },
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{ }
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{ }
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};
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};
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MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
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MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
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static void msm8226_clock_override(void)
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{
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mmss_axi_clk_src.freq_tbl = ftbl_mmss_axi_clk_msm8226;
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vfe0_clk_src.freq_tbl = ftbl_camss_vfe_vfe0_clk_msm8226;
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mdp_clk_src.freq_tbl = ftbl_mdss_mdp_clk_msm8226;
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vcodec0_clk_src.freq_tbl = ftbl_venus0_vcodec0_clk_msm8226;
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mclk0_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
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mclk1_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
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cpp_clk_src.freq_tbl = ftbl_camss_vfe_cpp_clk_msm8226;
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}
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static int mmcc_msm8974_probe(struct platform_device *pdev)
|
static int mmcc_msm8974_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct regmap *regmap;
|
struct regmap *regmap;
|
||||||
|
const struct qcom_cc_desc *desc;
|
||||||
|
|
||||||
regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
|
desc = of_device_get_match_data(&pdev->dev);
|
||||||
|
if (!desc)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
regmap = qcom_cc_map(pdev, desc);
|
||||||
if (IS_ERR(regmap))
|
if (IS_ERR(regmap))
|
||||||
return PTR_ERR(regmap);
|
return PTR_ERR(regmap);
|
||||||
|
|
||||||
clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
|
if (desc == &mmcc_msm8974_desc) {
|
||||||
clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
|
clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
|
||||||
|
clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
|
||||||
|
} else {
|
||||||
|
msm8226_clock_override();
|
||||||
|
}
|
||||||
|
|
||||||
return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
|
return qcom_cc_really_probe(pdev, desc, regmap);
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct platform_driver mmcc_msm8974_driver = {
|
static struct platform_driver mmcc_msm8974_driver = {
|
||||||
|
|
Loading…
Reference in a new issue